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1. 发明申请

US20050146045A1 Method for forming tungsten contact plug 有权
标题翻译：形成钨接触塞的方法
公开(公告)号：US20050146045A1
公开(公告)日：2005-07-07
申请号：US11002682
申请日：2004-12-03
申请人： Ji-Soon Park , Hyun-Seok Lim , Eung-Joon Lee , Jung-Wook Kim
发明人： Ji-Soon Park , Hyun-Seok Lim , Eung-Joon Lee , Jung-Wook Kim
IPC分类号： H01L21/28 , H01L21/285 , H01L21/44 , H01L21/768
CPC分类号： H01L21/28562 , H01L21/76843 , H01L21/76844 , H01L21/76876 , H01L21/76879 , H01L2221/1089
摘要： A method for forming a tungsten contact plug of a semiconductor device including depositing an insulating layer on a semiconductor substrate, etching the insulating layer to form a contact hole, which exposes a conductive region, forming a barrier layer on the semiconductor substrate having the contact hole, changing characteristics of a portion of the barrier layer on the insulating layer and the portion of the barrier layer in the contact hold such that the characteristics between the barrier layer on the insulating layer and the barrier layer in the contact hole differ, depositing a tungsten layer for forming the tungsten contact plug, on the barrier layer, and removing the tungsten layer from the upper portion of the insulating layer to planarize the semiconductor device.
摘要翻译：一种用于形成半导体器件的钨接触插塞的方法，包括在半导体衬底上沉积绝缘层，蚀刻绝缘层以形成接触孔，其暴露导电区域，在具有接触孔的半导体衬底上形成阻挡层改变绝缘层上的阻挡层的一部分和接触保持部中阻挡层的部分的特性，使得绝缘层上的阻挡层与接触孔中的阻挡层之间的特性不同，沉积钨在阻挡层上形成钨接触塞的层，以及从绝缘层的上部去除钨层以使半导体器件平坦化。

2. 发明授权

US07199019B2 Method for forming tungsten contact plug 有权
标题翻译：形成钨接触塞的方法
公开(公告)号：US07199019B2
公开(公告)日：2007-04-03
申请号：US11002682
申请日：2004-12-03
申请人： Ji-Soon Park , Hyun-Seok Lim , Eung-Joon Lee , Jung-Wook Kim
发明人： Ji-Soon Park , Hyun-Seok Lim , Eung-Joon Lee , Jung-Wook Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/28562 , H01L21/76843 , H01L21/76844 , H01L21/76876 , H01L21/76879 , H01L2221/1089
摘要： A method for forming a tungsten contact plug of a semiconductor device including depositing an insulating layer on a semiconductor substrate, etching the insulating layer to form a contact hole, which exposes a conductive region, forming a barrier layer on the semiconductor substrate having the contact hole, changing characteristics of a portion of the barrier layer on the insulating layer and the portion of the barrier layer in the contact hold such that the characteristics between the barrier layer on the insulating layer and the barrier layer in the contact hole differ, depositing a tungsten layer for forming the tungsten contact plug, on the barrier layer, and removing the tungsten layer from the upper portion of the insulating layer to planarize the semiconductor device.
摘要翻译：一种用于形成半导体器件的钨接触插塞的方法，包括在半导体衬底上沉积绝缘层，蚀刻绝缘层以形成接触孔，其暴露导电区域，在具有接触孔的半导体衬底上形成阻挡层改变绝缘层上的阻挡层的一部分和接触保持部中阻挡层的部分的特性，使得绝缘层上的阻挡层与接触孔中的阻挡层之间的特性不同，沉积钨在阻挡层上形成钨接触塞的层，以及从绝缘层的上部去除钨层以使半导体器件平坦化。

3. 发明授权

US07311109B2 Method for cleaning a processing chamber and method for manufacturing a semiconductor device 有权
标题翻译：用于清洁处理室的方法和用于制造半导体器件的方法
公开(公告)号：US07311109B2
公开(公告)日：2007-12-25
申请号：US10606512
申请日：2003-06-26
申请人： Jung-wook Kim , Hyeon-Deok Lee , Jin-Gi Hong , Ji-Soon Park , Eung-Joon Lee
发明人： Jung-wook Kim , Hyeon-Deok Lee , Jin-Gi Hong , Ji-Soon Park , Eung-Joon Lee
IPC分类号： B08B9/00 , H01L21/00
CPC分类号： C23C16/4405 , C23C16/0245 , H01L21/02063 , H01L21/76814 , Y10S438/905
摘要： A method for cleaning a processing chamber and manufacturing a semiconductor device by removing impurities from a substrate in the processing chamber with a plasma of a first gas including hydrogen gas. After the substrate is removed from the processing chamber, the processing chamber is etched with the plasma of a non-hydrogenous second gas. Thus, the etching selectivity can be improved and the particles are prevented from depositing and/or forming on the substrate.
摘要翻译：一种清洗处理室的方法，并且利用包含氢气的第一气体的等离子体从处理室中的基板上除去杂质来制造半导体器件。在从处理室移除基板之后，用非氢气的第二气体的等离子体蚀刻处理室。因此，可以提高蚀刻选择性，并且防止颗粒在衬底上沉积和/或形成。

4. 发明授权

US06797618B2 Method for forming silicide film of a semiconductor device 失效
标题翻译：半导体器件的硅化物膜的形成方法
公开(公告)号：US06797618B2
公开(公告)日：2004-09-28
申请号：US10630570
申请日：2003-07-29
申请人： Eung-Joon Lee , In-Sun Park , Ji-Soon Park
发明人： Eung-Joon Lee , In-Sun Park , Ji-Soon Park
IPC分类号： H01L2144
CPC分类号： H01L21/0206 , H01L21/02063 , H01L21/28052 , H01L21/28518 , H01L21/324 , H01L29/665 , Y10S438/906 , Y10S438/963
摘要： A conductive pattern having a surface including silicon is formed on a substrate of a semiconductor device and a conduction region having a surface including silicon is formed in the substrate. A radio frequency etching process is performed ex-situ to remove impurities from a resultant structure and to improve surface characteristics of the conduction region. Residues generated during the radio frequency etching process are removed from the conductive pattern and the conduction region by a cleaning process. A metal film is formed on the conductive pattern and the conduction region. A silicide film is formed on the conductive pattern and the conduction region by reacting metal of the metal film and silicon in the conductive pattern and the conduction region. With a radio frequency sputtering process and a wet cleaning process, a metal silicide film having a uniform phase may be stably formed.
摘要翻译：在半导体器件的衬底上形成具有包括硅的表面的导电图案，并且在衬底中形成具有包括硅的表面的导电区域。非原位地进行射频蚀刻处理以从所得结构中去除杂质并改善导电区域的表面特性。在射频蚀刻工艺中产生的残留物通过清洁处理从导电图案和导电区域中去除。在导电图案和导电区域上形成金属膜。通过金属膜的金属和导电图案中的硅和导电区域之间的反应，在导电图案和导电区域上形成硅化物膜。通过射频溅射法和湿式清洗法，可以稳定地形成具有均匀相的金属硅化物膜。

5. 发明授权

US06329276B1 Method of forming self-aligned silicide in semiconductor device 有权
标题翻译：在半导体器件中形成自对准硅化物的方法
公开(公告)号：US06329276B1
公开(公告)日：2001-12-11
申请号：US09392470
申请日：1999-09-09
申请人： Ja-Hum Ku , Soo-Geun Lee , Chul-Sung Kim , Tae-Wook Seo , Eung-Joon Lee , Joo-Hyuk Chung
发明人： Ja-Hum Ku , Soo-Geun Lee , Chul-Sung Kim , Tae-Wook Seo , Eung-Joon Lee , Joo-Hyuk Chung
IPC分类号： H01L213205
CPC分类号： H01L29/665 , H01L21/28518
摘要： There is provided a semiconductor device fabrication method. In the method, a gate layer is formed on a semiconductor substrate and patterned to form a first resultant structure, a metal layer is formed on the first resultant structure, a capping layer is formed on the metal layer, a metal silicide is formed on the gate layer by heating the substrate at a first temperature, unreacted metal layer and first capping layer are removed to form a second resultant structure, a second capping layer is formed on the second resultant structure, and the substrate is heated at a second temperature higher than the first temperature. The second capping layer suppresses a silicidation rate in the secondary heat treatment, thereby allowing a silicide of a good morphology to be achieved.
摘要翻译：提供了半导体器件制造方法。在该方法中，在半导体衬底上形成栅极层并形成第一结构，在第一结果结构上形成金属层，在金属层上形成覆盖层，在金属层上形成金属硅化物通过在第一温度下加热衬底，去除未反应的金属层和第一覆盖层以形成第二结构结构，在第二结构结构上形成第二覆盖层，并且将衬底在高于第一个温度。第二覆盖层抑制二次热处理中的硅化率，从而实现良好形态的硅化物。

6. 发明申请

US20060068585A1 Method for forming a metal silicide layer in a semiconductor device 有权
公开(公告)号：US20060068585A1
公开(公告)日：2006-03-30
申请号：US11280425
申请日：2005-11-16
申请人： Eung-Joon Lee , In-Sun Park , Kwan-Jong Roh
发明人： Eung-Joon Lee , In-Sun Park , Kwan-Jong Roh
IPC分类号： H01L21/4763
CPC分类号： H01L29/6653 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/665
摘要： On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.

7. 发明授权

US07375025B2 Method for forming a metal silicide layer in a semiconductor device 有权
标题翻译：在半导体器件中形成金属硅化物层的方法
公开(公告)号：US07375025B2
公开(公告)日：2008-05-20
申请号：US11280425
申请日：2005-11-16
申请人： Eung-Joon Lee , In-Sun Park , Kwan-Jong Roh
发明人： Eung-Joon Lee , In-Sun Park , Kwan-Jong Roh
IPC分类号： H01L21/4763
CPC分类号： H01L29/6653 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/665
摘要： On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.
摘要翻译：在衬底的第一和第二区域上分别形成包括第一栅极和第一间隔物的第一栅极结构，以及包括第二栅电极和第二间隔物的第二栅极结构。将第一和第二间隔物移除到不同的深度，使得第一和第二栅极的侧部具有不同的暴露厚度。在包括第一和第二栅极结构的第一和第二区域上形成金属硅化物层。形成在第二栅电极上的金属硅化物层具有大于形成在第一栅电极上的金属硅化物层的第一厚度的第二厚度。所得N型和P型MOS晶体管的栅极结构中的间隔物被去除到不同的厚度，从而最小化栅极结构中的变形，并且还改善栅电极的电特性和热稳定性。

8. 发明授权

US07566667B2 Methods of fabricating a semiconductor device having a barrier metal layer and devices formed thereby 失效
标题翻译：制造具有阻挡金属层的半导体器件的方法和由此形成的器件
公开(公告)号：US07566667B2
公开(公告)日：2009-07-28
申请号：US11284653
申请日：2005-11-22
申请人： Eung-Joon Lee , Hyun-Young Kim , In-Sun Park , Hyun-Deok Lee
发明人： Eung-Joon Lee , Hyun-Young Kim , In-Sun Park , Hyun-Deok Lee
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/3003 , H01L21/28518 , H01L21/28556 , H01L29/665 , H01L29/78
摘要： A semiconductor device is formed by forming a gate region, including a gate oxide layer, and impurity diffusion regions on a semiconductor substrate, forming a barrier metal layer on the gate region and the impurity diffusion regions of the semiconductor substrate, forming a passivation layer at an interface between the semiconductor substrate and the gate oxide layer to remove defects of the gate oxide layer, and then performing a nitridation process to remove impurities from the semiconductor substrate.
摘要翻译：半导体器件通过在半导体衬底上形成包括栅极氧化层的栅极区域和杂质扩散区域形成，在栅极区域和半导体衬底的杂质扩散区域上形成阻挡金属层，形成钝化层半导体衬底和栅极氧化物层之间的界面，以去除栅极氧化物层的缺陷，然后进行氮化处理以从半导体衬底去除杂质。

9. 发明申请

US20060113615A1 Methods of fabricating a semiconductor device having a barrier metal layer and devices formed thereby 失效
公开(公告)号：US20060113615A1
公开(公告)日：2006-06-01
申请号：US11284653
申请日：2005-11-22
申请人： Eung-Joon Lee , Hyun-Young Kim , In-Sun Park , Hyun-Deok Lee
发明人： Eung-Joon Lee , Hyun-Young Kim , In-Sun Park , Hyun-Deok Lee
IPC分类号： H01L21/8238 , H01L29/94
CPC分类号： H01L21/3003 , H01L21/28518 , H01L21/28556 , H01L29/665 , H01L29/78
摘要： A semiconductor device is formed by forming a gate region, including a gate oxide layer, and impurity diffusion regions on a semiconductor substrate, forming a barrier metal layer on the gate region and the impurity diffusion regions of the semiconductor substrate, forming a passivation layer at an interface between the semiconductor substrate and the gate oxide layer to remove defects of the gate oxide layer, and then performing a nitridation process to remove impurities from the semiconductor substrate.

10. 发明授权

US07005373B2 Method for forming a metal silicide layer in a semiconductor device 有权
标题翻译：在半导体器件中形成金属硅化物层的方法
公开(公告)号：US07005373B2
公开(公告)日：2006-02-28
申请号：US10790921
申请日：2004-03-02
申请人： Eung-Joon Lee , In-Sun Park , Kwan-Jong Roh
发明人： Eung-Joon Lee , In-Sun Park , Kwan-Jong Roh
IPC分类号： H01L21/4763
CPC分类号： H01L29/6653 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/665
摘要： On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.
摘要翻译：在衬底的第一和第二区域上分别形成包括第一栅极和第一间隔物的第一栅极结构，以及包括第二栅电极和第二间隔物的第二栅极结构。将第一和第二间隔物移除到不同的深度，使得第一和第二栅极的侧部具有不同的暴露厚度。在包括第一和第二栅极结构的第一和第二区域上形成金属硅化物层。形成在第二栅电极上的金属硅化物层具有大于形成在第一栅电极上的金属硅化物层的第一厚度的第二厚度。所得N型和P型MOS晶体管的栅极结构中的间隔物被去除到不同的厚度，从而最小化栅极结构中的变形，并且还改善栅电极的电特性和热稳定性。

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