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1. 发明申请

US20050027951A1 Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency 有权
标题翻译：支持非均匀内存多级条带化以最大化并发性的方法
公开(公告)号：US20050027951A1
公开(公告)日：2005-02-03
申请号：US10928046
申请日：2004-08-27
申请人： Gary Piccirillo , John MacLaren , Robert Lester , John Larson , Jerome Johnson , Benjamin Clark
发明人： Gary Piccirillo , John MacLaren , Robert Lester , John Larson , Jerome Johnson , Benjamin Clark
IPC分类号： G06F11/00 , G06F11/16 , G06F12/00
CPC分类号： G11C29/846 , G11C5/04 , G11C29/74 , G11C29/886 , G11C2029/0409 , G11C2029/0411
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。主机/数据控制器还交织与多个存储器模块中的每一个相关联的多个通道上的数据。

2. 发明申请

US20060085671A1 Error indication in a raid memory system 失效
标题翻译：突袭存储系统中的错误指示
公开(公告)号：US20060085671A1
公开(公告)日：2006-04-20
申请号：US11291243
申请日：2005-12-01
申请人： Tim Majni , Gary Piccirillo , John MacLaren , Robert Lester , John Larson , Jerome Johnson , Benjamin Clark , Patrick Ferguson , Siamak Tavallaei , Jeffrey Autor , Christian Post , Dan Zink , Jeffery Galloway , Bret Roscoe
发明人： Tim Majni , Gary Piccirillo , John MacLaren , Robert Lester , John Larson , Jerome Johnson , Benjamin Clark , Patrick Ferguson , Siamak Tavallaei , Jeffrey Autor , Christian Post , Dan Zink , Jeffery Galloway , Bret Roscoe
IPC分类号： G06F11/00
CPC分类号： G06F11/328 , G06F11/108 , G06F11/1092 , G06F2211/1052
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。主机/数据控制器还交织与多个存储器模块中的每一个相关联的多个通道上的数据。系统实施错误中断控制，ECC错误报告，响应命令错误的墨盒错误关闭程序，每个DIMM的未使用的段中的错误信息的存储，热插拔过程指示器和存储卡和DIMM的远程标记功能。

3. 发明申请

US20050193166A1 Memory latency and bandwidth optimizations 失效
标题翻译：内存延迟和带宽优化
公开(公告)号：US20050193166A1
公开(公告)日：2005-09-01
申请号：US10652943
申请日：2003-08-29
申请人： Jerome Johnson , Benjamin Clark , Gary Piccirillo , John MacLaren
发明人： Jerome Johnson , Benjamin Clark , Gary Piccirillo , John MacLaren
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F13/1642
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. To optimize memory bandwidth and reduce memory latency, various techniques are implemented in the present RAID system. Present techniques include providing dual memory arbiters, sorting read cycles by chip select or bank address, providing programmable upper and lower boundary registers to facilitate programmable memory mapping, and striping and interleaving memory data to provide a burst length of one.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。主机/数据控制器还交织与多个存储器模块中的每一个相关联的多个通道上的数据。为了优化存储器带宽并减少内存延迟，在本RAID系统中实现了各种技术。现有技术包括提供双存储器仲裁器，通过芯片选择或库地址排序读取周期，提供可编程的上限和下限边界寄存器以便于可编程存储器映射，以及条带化和交织存储器数据以提供一个突发长度。

4. 发明授权

US07793010B2 Bus system with multiple modes of operation 有权
标题翻译：总线系统具有多种运行模式
公开(公告)号：US07793010B2
公开(公告)日：2010-09-07
申请号：US11285243
申请日：2005-11-22
申请人： David M. Olson , Gary Piccirillo , Peter B. Chon
发明人： David M. Olson , Gary Piccirillo , Peter B. Chon
IPC分类号： G06F3/00 , G06F13/36
CPC分类号： G06F13/4282 , G06F2213/0026
摘要： An apparatus and a computer-implemented method for processing data in a bus system component. The bus system component is configured to operate in one of an endpoint mode and a root complex mode. Responsive to configuring the bus system component to operate in endpoint mode, the data is processed through the bus system component according to an endpoint process. Responsive to configuring the bus system component to operate in root complex mode, the data is transferred through the bus system component according to a root complex mode. In an illustrative example, the bus system component is a peripheral control interconnect express component.
摘要翻译：一种用于处理总线系统组件中的数据的装置和计算机实现的方法。总线系统组件被配置为在端点模式和根复合模式之一下操作。响应于将总线系统组件配置为在端点模式下操作，根据端点过程通过总线系统组件处理数据。响应于将总线系统组件配置为以根复合模式运行，数据通过总线系统组件根据根复合模式传输。在说明性示例中，总线系统组件是外围控制互连表达组件。

5. 发明申请

US20070130407A1 Bus system with multiple modes of operation 有权
标题翻译：总线系统具有多种运行模式
公开(公告)号：US20070130407A1
公开(公告)日：2007-06-07
申请号：US11285243
申请日：2005-11-22
申请人： David Olson , Gary Piccirillo , Peter Chon
发明人： David Olson , Gary Piccirillo , Peter Chon
IPC分类号： G06F13/14
CPC分类号： G06F13/4282 , G06F2213/0026
摘要： An apparatus and a computer-implemented method for processing data in a bus system component. The bus system component is configured to operate in one of an endpoint mode and a root complex mode. Responsive to configuring the bus system component to operate in endpoint mode, the data is processed through the bus system component according to an endpoint process. Responsive to configuring the bus system component to operate in root complex mode, the data is transferred through the bus system component according to a root complex mode. In an illustrative example, the bus system component is a peripheral control interconnect express component.
摘要翻译：一种用于处理总线系统组件中的数据的装置和计算机实现的方法。总线系统组件被配置为在端点模式和根复合模式之一下操作。响应于将总线系统组件配置为在端点模式下操作，根据端点过程通过总线系统组件处理数据。响应于将总线系统组件配置为以根复合模式运行，数据通过总线系统组件根据根复合模式传输。在说明性示例中，总线系统组件是外围控制互连表达组件。

6. 发明授权

US08458377B2 DMA engine capable of concurrent data manipulation 有权
标题翻译：能够并发数据操作的DMA引擎
公开(公告)号：US08458377B2
公开(公告)日：2013-06-04
申请号：US12718279
申请日：2010-03-05
申请人： Gary Piccirillo , David M. Olson
发明人： Gary Piccirillo , David M. Olson
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F21/72 , G06F21/85
摘要： Disclosed is a method and device for concurrently performing a plurality of data manipulation operations on data being transferred via a Direct Memory Access (DMA) channel managed by a DMA controller/engine. A Control Data Block (CDB) that controls where the data is retrieved from, delivered to, and how the plurality of data manipulation operations are performed may be fetched by the DMA controller. A CDB processor operating within the DMA controller may read the CDB and set up the data reads, data manipulation operations, and data writes in accord with the contents of the CDB. Data may be provided from one or more sources and data/modified data may be delivered to one or more destinations. While data is being channeled through the DMA controller, the DMA controller may concurrently perform a plurality of data manipulation operations on the data, such as, but not limited to: hashing, HMAC, fill pattern, LFSR, EEDP check, EEDP generation, XOR, encryption, and decryption. The data modification engines that perform the data manipulation operations may be implemented on the DMA controller such that the use of memory during data manipulation operations uses local RAM so as to avoid a need to access external memory during data manipulation operations.
摘要翻译：公开了一种用于同时对通过由DMA控制器/引擎管理的直接存储器访问（DMA）通道传送的数据进行多个数据操作操作的方法和装置。控制数据块（CDB）可以由DMA控制器获取控制从哪个数据被检索到，传递到哪里以及如何执行多个数据操作操作的控制数据块（CDB）。在DMA控制器中运行的CDB处理器可以读取CDB，并根据CDB的内容设置数据读取，数据操作操作和数据写入。数据可以从一个或多个源提供，并且数据/修改的数据可以被传送到一个或多个目的地。当数据通过DMA控制器传送时，DMA控制器可以同时对数据执行多个数据操作操作，例如但不限于：哈希，HMAC，填充模式，LFSR，EEDP检查，EEDP生成，XOR ，加密和解密。执行数据操作操作的数据修改引擎可以在DMA控制器上实现，使得在数据操作操作期间使用存储器使用本地RAM，以避免在数据操作操作期间访问外部存储器。

7. 发明申请

US20110219150A1 DMA ENGINE CAPABLE OF CONCURRENT DATA MANIPULATION 有权
标题翻译：可执行数据处理的DMA引擎
公开(公告)号：US20110219150A1
公开(公告)日：2011-09-08
申请号：US12718279
申请日：2010-03-05
申请人： Gary Piccirillo , David M. Olson
发明人： Gary Piccirillo , David M. Olson
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F21/72 , G06F21/85
摘要： Disclosed is a method and device for concurrently performing a plurality of data manipulation operations on data being transferred via a Direct Memory Access (DMA) channel managed by a DMA controller/engine. A Control Data Block (CDB) that controls where the data is retrieved from, delivered to, and how the plurality of data manipulation operations are performed may be fetched by the DMA controller. A CDB processor operating within the DMA controller may read the CDB and set up the data reads, data manipulation operations, and data writes in accord with the contents of the CDB. Data may be provided from one or more sources and data/modified data may be delivered to one or more destinations. While data is being channeled through the DMA controller, the DMA controller may concurrently perform a plurality of data manipulation operations on the data, such as, but not limited to: hashing, HMAC, fill pattern, LFSR, EEDP check, EEDP generation, XOR, encryption, and decryption. The data modification engines that perform the data manipulation operations may be implemented on the DMA controller such that the use of memory during data manipulation operations uses local RAM so as to avoid a need to access external memory during data manipulation operations.
摘要翻译：公开了一种用于同时对通过由DMA控制器/引擎管理的直接存储器访问（DMA）通道传送的数据进行多个数据操作操作的方法和装置。控制数据块（CDB）可以由DMA控制器获取控制从哪个数据被检索到，传递到哪里以及如何执行多个数据操作操作的控制数据块（CDB）。在DMA控制器中运行的CDB处理器可以读取CDB，并根据CDB的内容设置数据读取，数据操作操作和数据写入。数据可以从一个或多个源提供，并且数据/修改的数据可以被传送到一个或多个目的地。当数据通过DMA控制器传送时，DMA控制器可以同时对数据执行多个数据操作操作，例如但不限于：哈希，HMAC，填充模式，LFSR，EEDP检查，EEDP生成，XOR ，加密和解密。执行数据操作操作的数据修改引擎可以在DMA控制器上实现，使得在数据操作操作期间使用存储器使用本地RAM，以避免在数据操作操作期间访问外部存储器。

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