专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5707484A Method of accurate compositional analysis of dielectric films on semiconductors 失效
标题翻译：半导体介电膜准确组分分析方法
公开(公告)号：US5707484A
公开(公告)日：1998-01-13
申请号：US539029
申请日：1995-10-04
申请人： Jeremias D. Romero , Roger L. Alvis , Homi Fatemi
发明人： Jeremias D. Romero , Roger L. Alvis , Homi Fatemi
IPC分类号： H01L21/66 , H01L21/306
CPC分类号： H01L22/12
摘要： A method of accurately determining the composition of a dielectric film in a semiconductor device by performing a compositional analysis on a film only portion of the semiconductor device.
摘要翻译：一种通过对半导体器件的仅薄膜部分进行组成分析来准确地确定半导体器件中的电介质膜的组成的方法。

2. 发明授权

US5290588A TiW barrier metal process 失效
标题翻译： TiW阻隔金属工艺
公开(公告)号：US5290588A
公开(公告)日：1994-03-01
申请号：US812244
申请日：1991-12-19
申请人： Jeremias D. Romero , Homi Fatemi , Eugene A. Delenia , Muhib M. Khan
发明人： Jeremias D. Romero , Homi Fatemi , Eugene A. Delenia , Muhib M. Khan
IPC分类号： C23C14/14 , C23C14/58 , H01L21/48 , H01L23/498 , B05D5/12 , B05D3/02
CPC分类号： C23C14/5806 , C23C14/14 , C23C14/58 , C23C14/5893 , H01L21/4846 , H01L23/49866 , H01L2924/0002
摘要： An improved process is provided for forming a multilayer structure (18) suitable for tape automated bonding thereto or for forming contacts. In the process, a first layer (12) of aluminum is formed on a substrate (10), a second layer (14) of a TiW alloy is formed on the first layer of aluminum, and a third layer (16) of gold is formed on the second layer of the TiW alloy, to which third layer of gold bonding is done. The improvement comprises annealing the second layer of the TiW alloy in an inert atmosphere at a temperature less than about 500.degree. C. for a period of time sufficient to form a film of an Al--TiW phase (20), believed to comprise TiAl.sub.3, at the interface between the first layer of aluminum and the second layer of the TiW alloy. The annealing is done prior to forming the third layer of gold on the second layer of the TiW alloy.
摘要翻译：提供了一种改进的方法，用于形成适于胶带自动粘合或用于形成接触的多层结构（18）。在该方法中，在基板（10）上形成铝的第一层（12），在第一层铝上形成TiW合金的第二层（14），并且金的第三层（16）为形成在TiW合金的第二层上，进行第三层金键合。该改进包括在惰性气氛中在小于约500℃的温度下退火TiW合金的第二层足够长的时间以形成被认为包含TiAl 3的Al-TiW相（20）的膜，在第一层铝和第二层TiW合金之间的界面处。在TiW合金的第二层上形成第三层金之前进行退火。

3. 发明授权

US4931852A High thermal conductivity/low alpha emission molding compound containing high purity semiconductor filler and integrated circuit package 失效
标题翻译：高导热率/低α射线衍射化合物含有高纯度半导体填料和集成电路封装
公开(公告)号：US4931852A
公开(公告)日：1990-06-05
申请号：US180421
申请日：1988-04-12
申请人： Candice H. Brown , Homi Fatemi
发明人： Candice H. Brown , Homi Fatemi
IPC分类号： H01L23/29 , H01L23/42 , H01L23/556
CPC分类号： H01L23/556 , H01L23/295 , H01L23/42 , H01L2924/0002 , H01L2924/09701
摘要： The invention discloses an improved integrated circuit package having enhanced thermal conductivity comprising a molding or encapsulation resin having a semiconductor filler material. In a preferred embodiment, the semiconductor filler material comprises a high purity doped semiconductor to reduce alpha errors caused by alpha emisison normally caused by the use of fillers containing trace amounts of radioactive impurities and to provide enhanced thermal conductivity.
摘要翻译：本发明公开了一种改进的集成电路封装，其具有增强的热导率，包括具有半导体填充材料的模制或封装树脂。在优选实施例中，半导体填充材料包括高纯度掺杂半导体，以减少通常由使用含有痕量放射性杂质的填料引起的α辐射引起的α误差并提供增强的导热性。

4. 发明授权

US5994776A Interlevel dielectric with multiple air gaps between conductive lines of an integrated circuit 失效
标题翻译：集成电路的导线之间具有多个气隙的层间电介质
公开(公告)号：US5994776A
公开(公告)日：1999-11-30
申请号：US63481
申请日：1998-04-20
申请人： Peng Fang , Homi Fatemi
发明人： Peng Fang , Homi Fatemi
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/5329 , H01L23/53295 , H01L2924/0002
摘要： A method of forming low dielectric insulation between pairs of conductive lines separated by insulating material of a level of interconnection for integrated circuits by selectively removing portions of the insulating material to create spaces for containing a gas with a dielectric constant of slightly above 1. Preferably, the insulating material is a conformal source of silicon oxide, such as tetraethylorthosilicate. The resultant method forms an insulation separating the conductive lines whose composite dielectric constant with the gas in the spaces between the insulating material is not greater than about 3 over a predetermined distance. An integrated circuit having a plurality of semiconductor devices being interconnected by conductive lines separated by insulating material and spaces containing a gas, composite dielectric constant of which is not greater than about 3 over a predetermined distance.
摘要翻译：通过选择性地去除绝缘材料的部分以产生用于容纳介电常数略高于1的气体的空间，形成由用于集成电路的互连级别的绝缘材料隔开的导电线之间的低介电绝缘的方法。优选地，绝缘材料是氧化硅的保形源，例如原硅酸四乙酯。所得到的方法形成绝缘体，其绝缘材料的绝缘材料的复合介电常数与绝缘材料之间的间隔不大于约3°的预定距离的导线。一种具有多个半导体器件的集成电路，其通过由绝缘材料隔开的导线和包含气体的空间互相连接，复合介电常数在预定距离以上不大于约3。

5. 发明授权

US5808340A Short channel self aligned VMOS field effect transistor 失效
标题翻译：短沟道自对准VMOS场效应晶体管
公开(公告)号：US5808340A
公开(公告)日：1998-09-15
申请号：US714317
申请日：1996-09-18
申请人： Donald L. Wollesen , Homi Fatemi
发明人： Donald L. Wollesen , Homi Fatemi
IPC分类号： H01L21/336 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L29/78 , H01L29/66621 , H01L29/456 , H01L29/49
摘要： A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (L.sub.eff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom. Because of the V-shaped structure of the gate, the effective saturated length of the channel with drain voltage applied only extends from the edge of the source to just prior to the tip of the V-shaped structure in the interior of the semiconductor substrate. The drain side of the V-shaped structure becomes a depletion region due to the applied drain voltage. Due to this characteristic of such a structure, the surface width of the gate can be, for example, two or more times the distance of the desired channel length thereby permitting conventional lithography to be used to define the gate lengths much shorter than the lithographic limit.
摘要翻译：在半导体衬底中形成具有V形壁的沟槽或沟槽栅极的场效应晶体管，并且在V形壁上生长栅极氧化物到衬底表面，并且填充有诸如多晶硅的栅电极材料。优选地，在填充沟槽之前，V形壁的底部是圆形的。源极/漏极杂质可以扩散或注入到V形栅极的表面氧化物两侧的衬底区域中。触点在场隔离中被制成源极，漏极和栅极，以完成结构。所得到的FET结构包括具有常规源极和漏极的自对准V形栅极，该源极和漏极被场隔离包围，但具有小于栅极表面宽度的约一半的有效沟道长度（Leff）。优选地，V形门的会聚壁在圆形凹入的底部中。由于栅极的V形结构，所以施加漏极电压的沟道的有效饱和长度仅从源极的边缘延伸到半导体衬底内部的V形结构的尖端之前。 V形结构的漏极侧由于施加的漏极电压而变为耗尽区。由于这种结构的这种特性，栅极的表面宽度可以是例如期望沟道长度的两倍或更多倍的距离，从而允许常规光刻用于限定比光刻极限短的栅极长度。

6. 发明授权

US5960271A Short channel self-aligned VMOS field effect transistor 失效
标题翻译：短沟道自对准VMOS场效应晶体管
公开(公告)号：US5960271A
公开(公告)日：1999-09-28
申请号：US42786
申请日：1998-03-17
申请人： Donald L. Wollesen , Homi Fatemi
发明人： Donald L. Wollesen , Homi Fatemi
IPC分类号： H01L21/336 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/78
CPC分类号： H01L29/78 , H01L29/66621 , H01L29/456 , H01L29/49
摘要： A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (L.sub.eff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom. Because of the V-shaped structure of the gate, the effective saturated length of the channel with drain voltage applied only extends from the edge of the source to just prior to the tip of the V-shaped structure in the interior of the semiconductor substrate. The drain side of the V-shaped structure becomes a depletion region due to the applied drain voltage. Due to this characteristic of such a structure, the surface width of the gate can be, for example, two or more times the distance of the desired channel length thereby permitting conventional lithography to be used to define the gate lengths much shorter than the lithographic limit.
摘要翻译：在半导体衬底中形成具有V形壁的沟槽或沟槽栅极的场效应晶体管，并且在V形壁上生长栅极氧化物到衬底表面，并且填充有诸如多晶硅的栅电极材料。优选地，在填充沟槽之前，V形壁的底部是圆形的。源极/漏极杂质可以扩散或注入到V形栅极的表面氧化物两侧的衬底区域中。触点在场隔离中被制成源极，漏极和栅极，以完成结构。所得到的FET结构包括具有常规源极和漏极的自对准V形栅极，该源极和漏极被场隔离包围，但具有小于栅极表面宽度的约一半的有效沟道长度（Leff）。优选地，V形门的会聚壁在圆形凹入的底部中。由于栅极的V形结构，所以施加漏极电压的沟道的有效饱和长度仅从源极的边缘延伸到半导体衬底内部的V形结构的尖端之前。 V形结构的漏极侧由于施加的漏极电压而变为耗尽区。由于这种结构的这种特性，栅极的表面宽度可以是例如期望沟道长度的两倍或更多倍的距离，从而允许常规光刻用于限定比光刻极限短的栅极长度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式