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1. 发明授权

US06518793B2 Embedding of dynamic circuits in a static environment 失效
标题翻译：在静态环境中嵌入动态电路
公开(公告)号：US06518793B2
公开(公告)日：2003-02-11
申请号：US09815355
申请日：2001-03-22
申请人： Jens Leenstra , Hans-Werner Tast , Dieter Wendel , Peter Hofstee
发明人： Jens Leenstra , Hans-Werner Tast , Dieter Wendel , Peter Hofstee
IPC分类号： H03K1900
CPC分类号： G01R31/318577 , G01R31/318583 , G01R31/318586
摘要： The present invention relates to improvements concerning logic and timing verification as the testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment. The clocked macros comprising the dynamic logic circuit are bounded at both input and output by latches, keeping input and output signals to the clocked macro static. The static input signals are processed with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, and the dynamic logic output signal is converted back to a static signal by a set/reset latch such that it can be latched by the clock signal of the static embedding circuit. Thus, the analysis methods for timing and logic simulation during chip design can be the same as those used for static logic and, in particular, the LSSD testing methods can be used.
摘要翻译：本发明涉及关于逻辑和定时验证的改进，作为包括在静态环境中嵌入动态逻辑电路的硬件电路的可测试性。包含动态逻辑电路的时钟宏在锁存器的输入和输出两端都被限制，保持输入和输出信号到时钟宏。静态输入信号用波形格式化装置处理，以产生可用于动态逻辑电路的评估的波形，并且动态逻辑输出信号通过设置/复位锁存器转换回静态信号，使得它可以被静态嵌入电路的时钟信号锁存。因此，芯片设计中的定时和逻辑仿真分析方法可以与静态逻辑中使用的分析方法相同，特别是可以使用LSSD测试方法。

2. 发明授权

US07913132B2 System and method for scanning sequential logic elements 有权
标题翻译：用于扫描顺序逻辑元件的系统和方法
公开(公告)号：US07913132B2
公开(公告)日：2011-03-22
申请号：US12273985
申请日：2008-11-19
申请人： Tobias Gemmeke , Dieter Wendel , Holger Wetter , Jens Leenstra
发明人： Tobias Gemmeke , Dieter Wendel , Holger Wetter , Jens Leenstra
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： A digital system and method for scanning sequential logic elements are disclosed. The digital system may comprise a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; and at least one shadow engine, wherein the at least one shadow engine comprises a control circuit. At least some of the power domains may be interconnected to the scan chain with the scan enable switch, and the scan enable switch may control the scan mode by asserting a scan enable signal. The at least one power gated power domain with one or more sequential logic elements to be power gated may be bypassed via the at least one shadow engine.
摘要翻译：公开了用于扫描顺序逻辑元件的数字系统和方法。数字系统可以包括被分成多个功率域的多个顺序逻辑元件，其中至少一个功率域是功率选通; 配置用于处理扫描数据序列的扫描链; 配置成用于控制扫描模式的扫描使能开关; 和至少一个阴影引擎，其中所述至少一个阴影引擎包括控制电路。至少一些功率域可以与扫描使能开关互连到扫描链，并且扫描使能开关可以通过断言扫描使能信号来控制扫描模式。可以经由至少一个阴影引擎绕过具有一个或多个顺序逻辑元件以供电门控的至少一个电源门控功率域。

3. 发明授权

US07844799B2 Method and system for pipeline reduction 有权
标题翻译：减少管道的方法和系统
公开(公告)号：US07844799B2
公开(公告)日：2010-11-30
申请号：US09683383
申请日：2001-12-20
申请人： Jens Leenstra , Antje Mueller , Juergen Pille , Dieter Wendel
发明人： Jens Leenstra , Antje Mueller , Juergen Pille , Dieter Wendel
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/3873 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： A method and system for operating a high frequency out-of-order processor with increased pipeline length. A new scheme is disclosed to reduce the pipeline by the detection and exploitation of so called “no dependency” for an instruction. A “no dependency” signal tells that all required source data is available for the instruction at least one cycle before the source data valid bit(s) are inserted into the issue queue. Therefore, one or more stages of the pipeline are bypassed.
摘要翻译：一种用于操作具有增加的管道长度的高频无序处理器的方法和系统。公开了一种新方案，通过对指令的所谓“不依赖”的检测和利用来减少流水线。 “无依赖”信号指示在将源数据有效位插入到发出队列之前至少一个周期，所有必需的源数据可用于指令。因此，管道的一个或多个阶段被绕过。

4. 发明授权

US06829699B2 Rename finish conflict detection and recovery 失效
标题翻译：重新完成冲突检测和恢复
公开(公告)号：US06829699B2
公开(公告)日：2004-12-07
申请号：US09683391
申请日：2001-12-20
申请人： Jens Leenstra , Dieter Wendel
发明人： Jens Leenstra , Dieter Wendel
IPC分类号： G06F938
CPC分类号： G06F9/3838 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： An improved method and system for operating an out of order processor at a high frequency enabled by an increased pipeline length. It is proposed to shorten the pipeline by a considerable number of stages by accepting that a write after read conflict may occur, when directly after renaming, during the “read ROB” pipeline stage, all the information (tag, validity and data) is read from an Reorder Buffer ROB entry, and is next written, in a following pipeline stage “write RS”, into a reservation station (RS) entry. In order to assure the correctness of processing in particular in cases of dependencies, e.g., write after read conflicts a separate inventional add in logic covers these cases. The logic detects the write after read conflict case of an Instructional Execution Unit (IEU) writing into the particular entry that is selected by the renaming logic during “read ROB”. Then, a separate issue process selects the entries for which a conflict is reported and writes the data into the respective entry of the RS. This increases performance because those conflict cases are rather seldom compared to the broad majority of instructions to be found in a statistically determined average instruction flow.
摘要翻译：一种改进的方法和系统，用于通过增加的流水线长度在高频下操作无序处理器。建议通过接受在读取冲突之后写入，直接在重命名之后，在“读取ROB”流水线阶段期间，可以读取所有信息（标签，有效性和数据），缩短流水线来自重排序缓冲器ROB条目，并且在下一个流水线级“写入RS”中被写入保留站（RS）条目。为了确保处理的正确性，特别是在依赖性的情况下，例如在读取冲突之后写入，单独的发明逻辑将覆盖这些情况。该逻辑检测指令执行单元（IEU）写入读写冲突之后的写入到在“读取ROB”期间由重命名逻辑选择的特定条目。然后，单独的问题过程选择报告冲突的条目，并将数据写入RS的相应条目。这增加了性能，因为这些冲突案例与在统计确定的平均指令流程中找到的大多数指令相比很少。

5. 发明授权

US06918119B2 Method and system to improve usage of an instruction window buffer in multi-processor, parallel processing environments 失效
标题翻译：在多处理器并行处理环境中改进指令窗口缓冲区使用的方法和系统
公开(公告)号：US06918119B2
公开(公告)日：2005-07-12
申请号：US09838068
申请日：2001-04-19
申请人： Wilhelm E. Haller , Jens Leenstra , Rolf Sautter , Dieter Wendel , Friedrich-Christian Wernicke
发明人： Wilhelm E. Haller , Jens Leenstra , Rolf Sautter , Dieter Wendel , Friedrich-Christian Wernicke
IPC分类号： G06F5/10 , G06F9/38 , G06F3/00
CPC分类号： G06F5/10 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： The present invention relates to a method and system for determining the status of each entry in an instruction window buffer in multi-processor, parallel processing environments. A combinatorial circuit, which automatically generates active instruction window status information, is added to the buffer itself. This status information is used by a plurality of processes like renaming registers and issuing and committing instructions as an output associated with a respective buffer entry.
摘要翻译：本发明涉及一种用于在多处理器并行处理环境中确定指令窗口缓冲器中的每个条目的状态的方法和系统。自动生成活动指令窗口状态信息的组合电路被添加到缓冲器本身。该状态信息被诸如重命名寄存器和发出和提交指令之类的多个进程用作与相应缓冲器条目相关联的输出。

6. 发明授权

US06785781B2 Read/write alignment scheme for port reduction of multi-port SRAM cells 失效
标题翻译：用于多端口SRAM单元端口缩减的读/写对准方案
公开(公告)号：US06785781B2
公开(公告)日：2004-08-31
申请号：US09825072
申请日：2001-04-03
申请人： Jens Leenstra , Juergen Pille , Rolf Sautter , Dieter Wendel
发明人： Jens Leenstra , Juergen Pille , Rolf Sautter , Dieter Wendel
IPC分类号： G06F1200
CPC分类号： G06F9/3814 , G06F9/3802 , G11C8/16
摘要： A considerable amount of area can be saved according to the present invention by reducing the number of input ports and the number of output ports to the number n of concurrently intended array accesses. This remarkable reduction of ports and thus an extraordinary associated area saving can be achieved when some knowledge about array utilization is exploited: The array accesses are to be performed with concurrent accesses from at most k particular groups. A group is defined by a plurality of array accesses which have at most one access to the same port at a time. Then, for reading the read results are aligned according to a simple re-wiring scheme to the respective read requesters, whereas for writing the accesses are aligned prior to the array access according to the same or a similar scheme.
摘要翻译：根据本发明，通过将输入端口的数量和输出端口的数量减少到同时预期的阵列访问的数量n，可以节省相当多的面积。当利用关于阵列利用的一些知识时，可以实现端口的显着减少，从而实现非常相关的区域保存：阵列访问将由最多k个特定组的并发访问执行。一组由多个阵列访问定义，每次访问至多一次访问同一个端口。然后，为了读取，读取结果根据简单的重新布线方案对齐到相应的读取请求者，而对于写入，根据相同或相似的方案在阵列访问之前进行对齐。

7. 发明授权

US08312069B2 Permute unit and method to operate a permute unit 失效
标题翻译：允许单位和方法来操作一个置换单元
公开(公告)号：US08312069B2
公开(公告)日：2012-11-13
申请号：US11872811
申请日：2007-10-16
申请人： Tobias Gemmeke , Jens Leenstra , Dieter Wendel
发明人： Tobias Gemmeke , Jens Leenstra , Dieter Wendel
IPC分类号： G06F7/00
CPC分类号： G06F13/4217 , Y02D10/14 , Y02D10/151
摘要： A permute unit includes permute logic and a crossbar working in cycles defined by clocking signals and generates one valid output vector per cycle by treating two parallel input vectors per cycle. The permute unit is double pumped by performing two inner cycles per outer cycle defined by the clocking signals. In the first inner cycle, first halves of both input vectors are treated. In the second inner cycle, second halves of both input vectors are treated and a valid output vector is generated from the results of the treatments within the first and the second inner cycles.
摘要翻译：置换单元包括置换逻辑和交叉开关，其周期由定时信号定义，并且通过每个周期处理两个并行输入向量来产生每个周期的一个有效输出向量。置换单元通过每个外部周期执行两个内部循环由时钟信号定义来进行双重泵浦。在第一个内循环中，处理两个输入向量的前半部分。在第二内循环中，处理两个输入向量的第二半，并且从第一和第二内循环中的处理结果生成有效的输出向量。

8. 发明授权

US07228403B2 Method for handling 32 bit results for an out-of-order processor with a 64 bit architecture 有权
标题翻译：用于处理具有64位架构的乱序处理器的32位结果的方法
公开(公告)号：US07228403B2
公开(公告)日：2007-06-05
申请号：US09683351
申请日：2001-12-18
申请人： Petra Leber , Jens Leenstra , Wolfram Sauer , Dieter Wendel
发明人： Petra Leber , Jens Leenstra , Wolfram Sauer , Dieter Wendel
IPC分类号： G06F9/40 , G06F9/44
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/3017 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method for operating a processor having an architecture of a larger bitlength with a program comprising instructions compiled to produce instruction results of at least one smaller bitlength having the steps of detecting when in program order a first smaller bitlength instruction is to be dispatched which does not have a target register address as one of its sources, and adding a so_extract_instruction into an instruction stream before the smaller bitlength instruction. The extract instruction includes the steps of dispatching the extract instruction together with the following smaller bitlength instruction from an instruction queue into a Reservation Station, issuing the extract instruction to an Instruction Execution Unit (IEU) as soon as all source operand data is available and an IEU is available according to respective issue scheme, executing the extract instruction by an available IEU, setting an indication that the result of the instruction needs to be written into the result field of the instruction following the extract instruction, and writing the extract instruction result into the result field of the first instruction, and into all fields of operands being dependent of the first instruction.
摘要翻译：一种用于操作具有较大位长度的架构的处理器的方法，所述程序包括编译为产生至少一个较小位长度的指令结果的指令的程序，所述指令结果具有以下步骤：在程序顺序中检测何时将发送第一较小位长指令，将目标寄存器地址作为其源之一，并在较小的比特长指令之前将so_extract_instruction添加到指令流中。提取指令包括以下步骤：将提取指令与以下较小的比特长指令一起从指令队列发送到预留站，一旦所有源操作数数据可用，就将提取指令发送到指令执行单元（IEU），并且 IEU根据各自的发行方案可用，通过可用的IEU执行提取指令，将提示结果的指示需要写入到提取指令之后的指令的结果字段中，并将提取指令结果写入第一条指令的结果字段，以及依赖于第一条指令的操作数的所有字段。

9. 发明授权

US06725332B2 Hierarchical priority filter with integrated serialization for determining the entry with the highest priority in a buffer memory 失效
标题翻译：具有集成序列化的分层优先级过滤器，用于确定缓冲存储器中具有最高优先级的条目
公开(公告)号：US06725332B2
公开(公告)日：2004-04-20
申请号：US09681346
申请日：2001-03-22
申请人： Jens Leenstra , Antje Mueller , Juergen Pille , Dieter Wendel
发明人： Jens Leenstra , Antje Mueller , Juergen Pille , Dieter Wendel
IPC分类号： G06F1200
CPC分类号： G06F13/18
摘要： A storage device and a method for determining the entry with the highest priority in a buffer memory. The method is characterized by the steps of operating a plurality of priority subfilter circuits each of them covering a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority, and selecting the entry associated with the highest priority subgroup. The storage device is able to be allocated and deallocated repeatedly during processing program instructions in a computer system. The storage device is further characterized by an operator for operating a plurality of priority subfilter circuits. Each of priority subfilter circuits covers a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority. The storage device is still further characterized by a selector for selecting the entry associated with the highest priority subgroup.
摘要翻译：一种用于在缓冲存储器中确定具有最高优先级的条目的存储装置和方法。该方法的特征在于操作多个优先级子过滤器电路的步骤，每个优先级子过滤器电路覆盖总共条目的分离子组，并且每个选择具有最高子组优先级的条目，并且选择与最高优先级子组相关联的条目。在计算机系统中的处理程序指令期间，能够重新分配和释放存储设备。存储装置的特征还在于操作者操作多个优先级子滤波器电路。每个优先级子过滤器电路覆盖总共条目的分离子组，并且每个选择具有最高子组优先级的条目。存储装置的特征还在于：选择器，用于选择与最高优先级子组相关联的条目。

10. 发明申请

US20090135961A1 System and Method for Scanning Sequential Logic Elements 有权
标题翻译：用于扫描顺序逻辑元件的系统和方法
公开(公告)号：US20090135961A1
公开(公告)日：2009-05-28
申请号：US12273985
申请日：2008-11-19
申请人： Tobias Gemmeke , Dieter Wendel , Holger Wetter , Jens Leenstra
发明人： Tobias Gemmeke , Dieter Wendel , Holger Wetter , Jens Leenstra
IPC分类号： H04L27/06
CPC分类号： G01R31/318536
摘要： System and Method for Scanning Sequential Logic Elements A digital system and method for scanning sequential logic elements are disclosed. The digital system may comprise a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; and at least one shadow engine, wherein the at least one shadow engine comprises a control circuit. At least some of the power domains may be interconnected to the scan chain with the scan enable switch, and the scan enable switch may control the scan mode by asserting a scan enable signal. The at least one power gated power domain with one or more sequential logic elements to be power gated may be bypassed via the at least one shadow engine.
摘要翻译：用于扫描顺序逻辑元件的系统和方法公开了用于扫描顺序逻辑元件的数字系统和方法。数字系统可以包括被分成多个功率域的多个顺序逻辑元件，其中至少一个功率域是功率选通; 配置用于处理扫描数据序列的扫描链; 配置成用于控制扫描模式的扫描使能开关; 和至少一个阴影引擎，其中所述至少一个阴影引擎包括控制电路。至少一些功率域可以与扫描使能开关互连到扫描链，并且扫描使能开关可以通过断言扫描使能信号来控制扫描模式。可以经由至少一个阴影引擎绕过具有一个或多个顺序逻辑元件以供电门控的至少一个电源门控功率域。

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