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1. 发明授权

US08008161B2 Capacitor assemblies 有权
标题翻译：电容器组件
公开(公告)号：US08008161B2
公开(公告)日：2011-08-30
申请号：US11156908
申请日：2005-06-20
申请人： Jens Bachmann , Bernd Föste , Klaus Goller , Jakob Kriz
发明人： Jens Bachmann , Bernd Föste , Klaus Goller , Jakob Kriz
IPC分类号： H01L21/20
CPC分类号： H01L27/0805
摘要： A method for fabricating a capacitor arrangement which includes at least three electrodes is described. The capacitor arrangement is fabricated using a number of lithography methods that is smaller than the number of electrodes. A capacitor arrangement extending over more than two or more interlayers between metallization layers has a high capacitance per unit area and can be fabricated in a simple way is also described. The circuit arrangement has a high capacitance per unit area and can be fabricated in a simple way. An electrode layer is first patterned using a dry-etching process and residues of the electrode layer are removed using a wet-chemical process, making it possible to fabricate capacitors with excellent electrical properties.
摘要翻译：描述了一种制造包括至少三个电极的电容器装置的方法。使用小于电极数量的多种光刻方法制造电容器布置。在金属化层之间延伸超过两个或更多个中间层的电容器布置具有每单位面积的高电容，并且可以以简单的方式制造。电路布置具有每单位面积的高电容，并且可以以简单的方式制造。首先使用干蚀刻工艺对电极层进行图案化，并且使用湿化学工艺除去电极层的残余物，使得可以制造具有优异电性能的电容器。

2. 发明申请

US20050287755A1 Capacitor assemblies 有权
标题翻译：电容器组件
公开(公告)号：US20050287755A1
公开(公告)日：2005-12-29
申请号：US11156908
申请日：2005-06-20
申请人： Jens Bachmann , Bernd Foste , Klaus Goller , Jakob Kriz
发明人： Jens Bachmann , Bernd Foste , Klaus Goller , Jakob Kriz
IPC分类号： H01L27/08 , H01L21/339 , H01L21/20
CPC分类号： H01L27/0805
摘要： A method for fabricating a capacitor arrangement which includes at least three electrodes is described. The capacitor arrangement is fabricated using a number of lithography methods that is smaller than the number of electrodes. A capacitor arrangement extending over more than two or more interlayers between metallization layers has a high capacitance per unit area and can be fabricated in a simple way is also described. The circuit arrangement has a high capacitance per unit area and can be fabricated in a simple way. An electrode layer is first patterned using a dry-etching process and residues of the electrode layer are removed using a wet-chemical process, making it possible to fabricate capacitors with excellent electrical properties.
摘要翻译：描述了一种制造包括至少三个电极的电容器装置的方法。使用小于电极数量的多种光刻方法制造电容器布置。在金属化层之间延伸超过两个或更多个中间层的电容器布置具有每单位面积的高电容，并且可以以简单的方式制造。电路布置具有每单位面积的高电容，并且可以以简单的方式制造。首先使用干蚀刻工艺对电极层进行图案化，并且使用湿化学工艺除去电极层的残余物，使得可以制造具有优异电性能的电容器。

3. 发明授权

US08273658B2 Integrated circuit arrangement including vias having two sections, and method for producing the same 有权
标题翻译：包括具有两个部分的通孔的集成电路装置及其制造方法
公开(公告)号：US08273658B2
公开(公告)日：2012-09-25
申请号：US11575385
申请日：2005-08-25
申请人： Klaus Goller , Jakob Kriz
发明人： Klaus Goller , Jakob Kriz
IPC分类号： H01L21/44
CPC分类号： H01L21/76877 , H01L21/76804 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via.
摘要翻译：公开了一种包含通孔的集成电路装置。通孔具有具有大大倾斜侧壁的上部部分。通孔的下部具有大致垂直的侧壁。在一个实施例中，衬垫层在通孔的制造中用作硬掩模，并且限定通孔的部分的位置。

4. 发明申请

US20080303169A1 Integrated Circuit Arrangment Including Vias Having Two Sections, and Method For Producing the Same 有权
标题翻译：包括具有两个部分的通孔的集成电路布置及其制造方法
公开(公告)号：US20080303169A1
公开(公告)日：2008-12-11
申请号：US11575385
申请日：2005-08-25
申请人： Klaus Goller , Jakob Kriz
发明人： Klaus Goller , Jakob Kriz
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76877 , H01L21/76804 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via.
摘要翻译：公开了一种包含通孔的集成电路装置。通孔具有具有大大倾斜侧壁的上部部分。通孔的下部具有大致垂直的侧壁。在一个实施例中，衬垫层在通孔的制造中用作硬掩模，并且限定通孔的部分的位置。

5. 发明授权

US07060583B2 Method for manufacturing a bipolar transistor having a polysilicon emitter 有权
标题翻译：一种制造具有多晶硅发射极的双极晶体管的方法
公开(公告)号：US07060583B2
公开(公告)日：2006-06-13
申请号：US10757360
申请日：2004-01-13
申请人： Jakob Kriz , Martin Seck , Armin Tilke
发明人： Jakob Kriz , Martin Seck , Armin Tilke
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/66272 , H01L21/2257
摘要： In the inventive method for manufacturing a bipolar transistor having a polysilicon emitter, a collector region of a first conductivity type and, adjoining thereto, a basis region of a second conductivity type will be generated at first. At least one layer of an insulating material will now be applied, wherein the at least one layer is patterned such that at least one section of the basis region is exposed. Next, a layer of a polycrystalline semiconductor material of the first conductivity type, which is heavily doped with doping atoms, will be generated such that the exposed section is essentially covered. Now, a second layer of a highly conductive material on the layer of the polycrystalline semiconductor material will be generated in order to form an emitter double layer with the same. Thereupon, at least part of the doping atoms of the first conductivity type of the heavily doped polycrystalline semiconductor layer is caused to get into the basis region to generate an emitter region of the first conductivity type.
摘要翻译：在本发明的制造具有多晶硅发射极的双极晶体管的方法中，首先将产生第一导电类型的集电极区域，并与其邻接的第二导电类型的基极区域。现在将施加至少一层绝缘材料，其中图案化至少一个层使得基础区域的至少一个部分被暴露。接下来，将产生重掺杂掺杂原子的第一导电类型的多晶半导体材料层，使得暴露部分基本上被覆盖。现在，将产生多晶半导体材料层上的高导电材料的第二层，以便形成具有该多层半导体材料的发射极双层。因此，引起重掺杂多晶半导体层的第一导电类型的掺杂原子的至少一部分进入基区以产生第一导电类型的发射极区。

6. 发明授权

US07557444B2 Power-via structure for integration in advanced logic/smart-power technologies 有权
标题翻译：电源通道结构，用于集成先进的逻辑/智能电源技术
公开(公告)号：US07557444B2
公开(公告)日：2009-07-07
申请号：US11525107
申请日：2006-09-20
申请人： Achim Gratz , Jakob Kriz , Woong-Jae Chung
发明人： Achim Gratz , Jakob Kriz , Woong-Jae Chung
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A via structure is disclosed for use in a multi-layered semiconductor device, for forming electrical contacts between prescribed layers of the vertically aligned structures. The via structures include a plurality of adjacent frame shaped hole structures which extend between the prescribed layers of the device, and which are filled with metal to form frame shaped vias. The width of each of the sides of the frame is chosen to be equal to an integer multiple of half of the minimum pitch of the semiconductor processing, with the distance between adjacent frame shaped via structures being approximately equal to an integer multiple of half of the minimum pitch of the semiconductor processing.
摘要翻译：公开了一种用于多层半导体器件中的通孔结构，用于在垂直排列的结构的规定层之间形成电接触。通孔结构包括在装置的规定层之间延伸并且被金属填充以形成框形通孔的多个相邻的框状孔结构。框架的每个边的宽度被选择为等于半导体处理的最小间距的一半的整数倍，相邻的框架形通孔结构之间的距离近似等于半导体处理的一半的整数倍半导体处理的最小间距。

7. 发明申请

US20080067688A1 Power-via structure for integration in advanced logic/smart-power technologies 有权
标题翻译：电源通道结构，用于集成先进的逻辑/智能电源技术
公开(公告)号：US20080067688A1
公开(公告)日：2008-03-20
申请号：US11525107
申请日：2006-09-20
申请人： Achim Gratz , Jakob Kriz , Woong-Jae Chung
发明人： Achim Gratz , Jakob Kriz , Woong-Jae Chung
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A via structure is disclosed for use in a multi-layered semiconductor device, for forming electrical contacts between prescribed layers of the vertically aligned structures. The via structures include a plurality of adjacent frame shaped hole structures which extend between the prescribed layers of the device, and which are filled with metal to form frame shaped vias. The width of each of the sides of the frame is chosen to be equal to an integer multiple of half of the minimum pitch of the semiconductor processing, with the distance between adjacent frame shaped via structures being approximately equal to an integer multiple of half of the minimum pitch of the semiconductor processing.
摘要翻译：公开了一种用于多层半导体器件中的通孔结构，用于在垂直排列的结构的规定层之间形成电接触。通孔结构包括在装置的规定层之间延伸并且被金属填充以形成框形通孔的多个相邻的框状孔结构。框架的每个边的宽度被选择为等于半导体处理的最小间距的一半的整数倍，相邻的框架形通孔结构之间的距离近似等于半导体处理的一半的整数倍半导体处理的最小间距。

8. 发明授权

US06844584B2 Memory cell, memory cell configuration and fabrication method 有权
标题翻译：存储单元，存储单元配置和制造方法
公开(公告)号：US06844584B2
公开(公告)日：2005-01-18
申请号：US09927573
申请日：2001-08-09
申请人： Herbert Palm , Josef Willer , Achim Gratz , Jakob Kriz , Mayk Roehrich
发明人： Herbert Palm , Josef Willer , Achim Gratz , Jakob Kriz , Mayk Roehrich
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.
摘要翻译：每个存储单元是存储晶体管，其设置在半导体本体的顶侧，并且具有布置在形成于半导体材料中的源极区域和漏极区域之间的沟槽中的栅电极。栅电极通过介电材料与半导体材料分离。至少在源极区域和栅极电极之间以及漏极区域和栅极电极之间，存在氧化物 - 氧化物 - 氧化物层序列。层序列是为了在源极和漏极处俘获电荷载体而提供的。

9. 发明申请

US20070194301A1 Semiconductor arrangement with non-volatile memories 审中-公开
标题翻译：具有非易失性存储器的半导体装置
公开(公告)号：US20070194301A1
公开(公告)日：2007-08-23
申请号：US10580881
申请日：2004-11-24
申请人： Recai Sezi , Andreas Walter , Reimund Engl , Anna Maltenberger , Christine Dehm , Sitaram Arkalgud , Igor Kasko , Joachim Nuetzel , Jakob Kriz , Thomas Mikolajick , Cay-Uwe Pinnow
发明人： Recai Sezi , Andreas Walter , Reimund Engl , Anna Maltenberger , Christine Dehm , Sitaram Arkalgud , Igor Kasko , Joachim Nuetzel , Jakob Kriz , Thomas Mikolajick , Cay-Uwe Pinnow
IPC分类号： H01L51/00 , H01L21/8232
CPC分类号： H01L51/0036 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/28 , H01L51/0051 , H01L51/0062 , H01L51/0595
摘要： One aspect of the invention relates to a semiconductor arrangement having at least one nonvolatile memory cell which has a first electrode comprising at least two layers; and having an organic material, the organic material forming a compound with that layer of the first electrode which is in direct contact. One aspect of the invention furthermore relates to a method for producing the nonvolatile memory cell, a semiconductor arrangement having a plurality of memory cells according to the invention, and a method for producing the same.
摘要翻译：本发明的一个方面涉及具有至少一个非易失性存储单元的半导体装置，其具有包括至少两层的第一电极; 并且具有有机材料，所述有机材料与所述第一电极的所述层直接接触形成化合物。本发明的一个方面还涉及一种用于制造非易失性存储单元的方法，具有根据本发明的多个存储单元的半导体装置及其制造方法。

10. 发明授权

US09064875B2 Semiconductor structure and method for making same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09064875B2
公开(公告)日：2015-06-23
申请号：US13300692
申请日：2011-11-21
申请人： Jakob Kriz , Norbert Urbansky
发明人： Jakob Kriz , Norbert Urbansky
IPC分类号： H01L21/4763 , H01L23/532 , H01L21/768 , H01L23/00
CPC分类号： H01L23/53223 , H01L21/76831 , H01L21/76834 , H01L21/76843 , H01L21/76856 , H01L21/76864 , H01L21/76873 , H01L21/76885 , H01L23/53238 , H01L23/53252 , H01L23/53295 , H01L24/03 , H01L24/05 , H01L2224/03462 , H01L2224/03848 , H01L2224/0391 , H01L2224/05557 , H01L2224/05567 , H01L2224/05573 , H01L2224/05647 , H01L2924/00014 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2224/05552
摘要： Embodiments relate to a method for making a semiconductor structure, the method comprising: forming a seed layer in direct contact with a dielectric material; forming a masking layer over the seed layer; patterning the masking layer to expose the seed layer; forming a fill layer over the exposed seed layer; and causing the seed layer to react with the dielectric layer to form a barrier layer between the fill layer and the dielectric layer.
摘要翻译：实施例涉及制造半导体结构的方法，所述方法包括：形成与电介质材料直接接触的晶种层; 在种子层上形成掩模层; 图案化掩模层以暴露种子层; 在所述暴露的种子层上形成填充层; 并使种子层与介电层反应，以在填充层和介电层之间形成阻挡层。

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