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1. 发明授权

US08304271B2 Integrated circuit having a bulk acoustic wave device and a transistor 有权
标题翻译：具有体声波器件和晶体管的集成电路
公开(公告)号：US08304271B2
公开(公告)日：2012-11-06
申请号：US12469326
申请日：2009-05-20
申请人： Jenn Hwa Huang , Bruce M. Green
发明人： Jenn Hwa Huang , Bruce M. Green
IPC分类号： H01L21/00
CPC分类号： H01L29/812 , H01L29/2003 , H01L29/41725 , H01L29/66856 , H01L29/7786
摘要： A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.
摘要翻译：体GaN层位于衬底的第一表面上，其中体GaN层具有GaN晶体管区和体声波（BAW）器件区。源极/漏极层在GaN晶体管区域中的体GaN层的第一表面之上。在源极/漏极层上形成栅电极。第一BAW电极形成在BAW器件区域中的体GaN层的第一表面上。在衬底的与衬底的第一表面相对的第二表面上形成开口，该第一表面延伸穿过衬底并暴露与体GaN层的第一表面相对的体GaN层的第二表面。在体GaN层的第二表面上的开口内形成第二BAW电极。

2. 发明授权

US09153448B2 Semiconductor device with selectively etched surface passivation 有权
公开(公告)号：US09153448B2
公开(公告)日：2015-10-06
申请号：US14601804
申请日：2015-01-21
申请人： Bruce M. Green , Darrell G. Hill , Jenn Hwa Huang , Karen E. Moore
发明人： Bruce M. Green , Darrell G. Hill , Jenn Hwa Huang , Karen E. Moore
IPC分类号： H01L21/285 , H01L21/311 , H01L29/40 , H01L29/66 , H01L29/778 , H01L29/06 , H01L29/10 , H01L29/812 , H01L29/20
CPC分类号： H01L21/28581 , H01L21/31111 , H01L21/31116 , H01L29/0615 , H01L29/1029 , H01L29/2003 , H01L29/402 , H01L29/66462 , H01L29/7787 , H01L29/812
摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.

3. 发明申请

US20130341678A1 Semiconductor Device with Selectively Etched Surface Passivation 有权
标题翻译：具有选择性蚀刻表面钝化的半导体器件
公开(公告)号：US20130341678A1
公开(公告)日：2013-12-26
申请号：US13533610
申请日：2012-06-26
申请人： Bruce M. Green , Darrell G. Hill , Jenn Hwa Huang , Karen E. Moore
发明人： Bruce M. Green , Darrell G. Hill , Jenn Hwa Huang , Karen E. Moore
IPC分类号： H01L29/812 , H01L29/778 , H01L21/311
CPC分类号： H01L21/28581 , H01L21/31111 , H01L21/31116 , H01L29/0615 , H01L29/1029 , H01L29/2003 , H01L29/402 , H01L29/66462 , H01L29/7787 , H01L29/812
摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.
摘要翻译：半导体器件包括被配置为包括沟道的半导体衬底，由半导体衬底支撑的栅极以控制通过沟道的电流;由半导体衬底支撑并包括其中设置栅极的开口的第一电介质层，以及第二电介质层，设置在所述沟道上的第一区域中的所述第一介电层和所述半导体衬底的表面之间。图案化第二电介质层，使得第一电介质层在通道上的第二区域中设置在半导体衬底的表面上。

4. 发明申请

US20150132932A1 SEMICONDUCTOR DEVICE WITH SELECTIVELY ETCHED SURFACE PASSIVATION 有权
标题翻译：具有选择性表面钝化的半导体器件
公开(公告)号：US20150132932A1
公开(公告)日：2015-05-14
申请号：US14601804
申请日：2015-01-21
申请人： Bruce M. Green , Darrell G. Hill , Jenn Hwa Huang , Karen E. Moore
发明人： Bruce M. Green , Darrell G. Hill , Jenn Hwa Huang , Karen E. Moore
IPC分类号： H01L21/285
CPC分类号： H01L21/28581 , H01L21/31111 , H01L21/31116 , H01L29/0615 , H01L29/1029 , H01L29/2003 , H01L29/402 , H01L29/66462 , H01L29/7787 , H01L29/812
摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.
摘要翻译：半导体器件包括被配置为包括沟道的半导体衬底，由半导体衬底支撑的栅极以控制通过沟道的电流;由半导体衬底支撑并包括其中设置栅极的开口的第一电介质层，以及第二电介质层，设置在所述沟道上的第一区域中的所述第一介电层和所述半导体衬底的表面之间。图案化第二电介质层，使得第一电介质层在通道上的第二区域中设置在半导体衬底的表面上。

5. 发明授权

US08946776B2 Semiconductor device with selectively etched surface passivation 有权
标题翻译：具有选择性蚀刻表面钝化的半导体器件
公开(公告)号：US08946776B2
公开(公告)日：2015-02-03
申请号：US13533610
申请日：2012-06-26
申请人： Bruce M. Green , Darrell G. Hill , Jenn Hwa Huang , Karen E. Moore
发明人： Bruce M. Green , Darrell G. Hill , Jenn Hwa Huang , Karen E. Moore
IPC分类号： H01L29/812
CPC分类号： H01L21/28581 , H01L21/31111 , H01L21/31116 , H01L29/0615 , H01L29/1029 , H01L29/2003 , H01L29/402 , H01L29/66462 , H01L29/7787 , H01L29/812
摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.
摘要翻译：半导体器件包括被配置为包括沟道的半导体衬底，由半导体衬底支撑的栅极以控制通过沟道的电流;由半导体衬底支撑并包括其中设置栅极的开口的第一电介质层，以及第二电介质层，设置在所述沟道上的第一区域中的所述第一介电层和所述半导体衬底的表面之间。图案化第二电介质层，使得第一电介质层在通道上的第二区域中设置在半导体衬底的表面上。

6. 发明授权

US09111868B2 Semiconductor device with selectively etched surface passivation 有权
标题翻译：具有选择性蚀刻表面钝化的半导体器件
公开(公告)号：US09111868B2
公开(公告)日：2015-08-18
申请号：US13533651
申请日：2012-06-26
申请人： Bruce M. Green , Darrell G. Hill , Jenn Hwa Huang , Karen E. Moore
发明人： Bruce M. Green , Darrell G. Hill , Jenn Hwa Huang , Karen E. Moore
IPC分类号： H01L21/338 , H01L21/285 , H01L29/40 , H01L29/66 , H01L29/778 , H01L29/06 , H01L29/10 , H01L21/311 , H01L29/812 , H01L29/20
CPC分类号： H01L29/778 , H01L21/28575 , H01L21/31111 , H01L21/31116 , H01L29/0615 , H01L29/1029 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/66462 , H01L29/7787 , H01L29/812
摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.
摘要翻译：半导体器件包括半导体衬底，其被配置为包括沟道，由半导体衬底支撑的第一和第二欧姆触点，与半导体衬底欧姆接触，并且彼此间隔开，以在第一和第二欧姆触点之间通过沟道，以及由半导体衬底支撑的第一和第二电介质层。第一和第二欧姆触点中的至少一个延伸穿过第一和第二电介质层中的相应开口。第二电介质层设置在第一电介质层和半导体衬底的表面之间，第二电介质层包括具有对第一介电层的干蚀刻剂的蚀刻选择性的湿蚀刻材料。

7. 发明授权

US08653558B2 Semiconductor device and method of making 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08653558B2
公开(公告)日：2014-02-18
申请号：US13273622
申请日：2011-10-14
申请人： Bruce M. Green , Jenn Hwa Huang , Weixiao Huang
发明人： Bruce M. Green , Jenn Hwa Huang , Weixiao Huang
IPC分类号： H01L29/66 , H01L21/337
CPC分类号： H01L29/7787 , H01L21/28264 , H01L29/2003 , H01L29/513 , H01L29/517 , H01L29/66462
摘要： In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate. The source and drain are on opposing sides of a channel region of a channel layer. The channel region is an upper portion of the channel layer. The channel layer comprises gallium nitride. The insulation layer is over the channel layer and has a first portion and a second portion. The first portion is nearer the drain than the source and has a first thickness. The second portion is nearer the source than drain and has the first thickness. The insulation layer has an opening through the insulation layer. The opening is between the first portion and the second portion.
摘要翻译：在一些实施例中，公开了具有源极，漏极，绝缘层，栅极电介质和栅极的金属绝缘体半导体异质结构场效应晶体管（MISHFET）。源极和漏极在沟道层的沟道区域的相对侧上。沟道区是沟道层的上部。沟道层包括氮化镓。绝缘层在沟道层上方并具有第一部分和第二部分。第一部分比源极更靠近漏极并具有第一厚度。第二部分比排水源更靠近源头并具有第一厚度。绝缘层具有穿过绝缘层的开口。开口位于第一部分和第二部分之间。

8. 发明申请

US20130341679A1 Semiconductor Device with Selectively Etched Surface Passivation 有权
公开(公告)号：US20130341679A1
公开(公告)日：2013-12-26
申请号：US13533651
申请日：2012-06-26
申请人： Bruce M. Green , Darrell G. Hill , Jenn Hwa Huang , Karen E. Moore
发明人： Bruce M. Green , Darrell G. Hill , Jenn Hwa Huang , Karen E. Moore
IPC分类号： H01L21/28 , H01L29/80
CPC分类号： H01L29/778 , H01L21/28575 , H01L21/31111 , H01L21/31116 , H01L29/0615 , H01L29/1029 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/66462 , H01L29/7787 , H01L29/812
摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.

9. 发明申请

US20130092947A1 SEMICONDUCTOR DEVICE AND METHOD OF MAKING 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130092947A1
公开(公告)日：2013-04-18
申请号：US13273622
申请日：2011-10-14
申请人： BRUCE M. GREEN , Jenn Hwa Huang , Weixiao Huang
发明人： BRUCE M. GREEN , Jenn Hwa Huang , Weixiao Huang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7787 , H01L21/28264 , H01L29/2003 , H01L29/513 , H01L29/517 , H01L29/66462
摘要： In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate. The source and drain are on opposing sides of a channel region of a channel layer. The channel region is an upper portion of the channel layer. The channel layer comprises gallium nitride. The insulation layer is over the channel layer and has a first portion and a second portion. The first portion is nearer the drain than the source and has a first thickness. The second portion is nearer the source than drain and has the first thickness. The insulation layer has an opening through the insulation layer. The opening is between the first portion and the second portion.
摘要翻译：在一些实施例中，公开了具有源极，漏极，绝缘层，栅极电介质和栅极的金属绝缘体半导体异质结构场效应晶体管（MISHFET）。源极和漏极在沟道层的沟道区域的相对侧上。沟道区是沟道层的上部。沟道层包括氮化镓。绝缘层在沟道层上方并具有第一部分和第二部分。第一部分比源极更靠近漏极并具有第一厚度。第二部分比排水源更靠近源头并具有第一厚度。绝缘层具有穿过绝缘层的开口。开口位于第一部分和第二部分之间。

10. 发明申请

US20090212374A1 SPACE EFFICIENT INTEGRATRED CIRCUIT WITH PASSIVE DEVICES 有权
标题翻译：空间有效的集成电路与被动设备
公开(公告)号：US20090212374A1
公开(公告)日：2009-08-27
申请号：US12037280
申请日：2008-02-26
申请人： Jenn Hwa Huang , Elizabeth C. Glass
发明人： Jenn Hwa Huang , Elizabeth C. Glass
IPC分类号： H01L27/06
CPC分类号： H01L27/08 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A multimodal integrated circuit (IC) is provided, comprising, first (74) and second (76) semiconductor (SC) devices, and first (78) and second (80) integrated passive devices (IPDs) coupled, respectively, to the first (74) and second (76) SC devices, wherein the first IPD (78) overlies the second SC device (76) and the second IPD (80) overlies the first SC device (74) chosen such that the underlying SC device (74, 76) is not active at the same time as its overlying IPD (80, 78). By placing the IPDs (78, 80) over the SC devices (76, 74) a compact IC layout is obtained. Since the overlying IPD (78, 80) and underlying SC (76, 74) are not active at the same time, undesirable cross-talk (68, 69) between the IPDs (78, 80) and the SC devices (76, 74) is avoided. This arrangement applies to any IC having multiple signal paths (RF1, RF2) where the IPDs (78, 80) of a first path (RF1, RF2) may be placed over the SC devices (76, 74) of a second path (RF2, RF1) not active at the same time. This is especially useful with high frequencies ICs.
摘要翻译：提供了一种多模式集成电路（IC），其包括第一（74）和第二（76）半导体（SC）器件以及第一（78）和第二（80）集成无源器件（IPD），分别耦合到第一（74）和第二（76）个SC设备，其中所述第一IPD（78）覆盖所述第二SC设备（76），并且所述第二IPD（80）覆盖所选择的所述第一SC设备（74），使得所述下面的SC设备，76）在上层IPD的同时不起作用（80,78）。通过将IPD（78,80）放置在SC设备（76,74）上，可以获得紧凑的IC布局。由于上覆IPD（78,80）和底层SC（76,74）同时不起作用，IPD（78,80）与SC设备（76,74）之间的不期望的串扰（68,69））。这种布置适用于具有多个信号路径（RF1，RF2）的任何IC，其中第一路径（RF1，RF2）的IPD（78,80）可以放置在第二路径（RF2，RF2）的SC设备（76,74）上，RF1）不同时激活。这对于高频IC尤其有用。

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