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1. 发明授权

US09558131B1 Integrated circuit with bonding circuits for bonding memory controllers 有权
标题翻译：具有用于连接存储器控制器的接合电路的集成电路
公开(公告)号：US09558131B1
公开(公告)日：2017-01-31
申请号：US13164426
申请日：2011-06-20
申请人： Jeffrey Schulz , Chiakang Sung , Michael H. M. Chu
发明人： Jeffrey Schulz , Chiakang Sung , Michael H. M. Chu
IPC分类号： G06F13/00
CPC分类号： G06F13/00 , G06F13/1678 , G06F13/1684 , G06F13/4022
摘要： An IC that includes a first memory controller, a second memory controller, and a first bonding circuit coupled to the first memory controller, where the first bonding circuit is a hard logic bonding circuit and is operable to coordinate memory control functions of the first memory controller and the second memory controller. In one implementation, the first memory controller is an N bits wide memory controller, the second memory controller is an M bits wide memory controller, and the first bonding circuit is operable to coordinate the memory control functions of the first memory controller and the second memory controller such that the first and second memory controllers together function as an N+M bits wide memory controller, where N and M are positive integers.
摘要翻译：一种IC，包括第一存储器控制器，第二存储器控制器和耦合到第一存储器控制器的第一接合电路，其中第一接合电路是硬逻辑接合电路，并且可操作以协调第一存储器控制器的存储器控制功能和第二存储器控制器。在一个实现中，第一存储器控制器是N位宽存储器控制器，第二存储器控制器是M位宽存储器控制器，并且第一接合电路可操作以协调第一存储器控制器和第二存储器的存储器控制功能控制器，使得第一和第二存储器控制器一起用作N + M位宽存储器控制器，其中N和M是正整数。

2. 发明授权

US09032162B1 Systems and methods for providing memory controllers with memory access request merging capabilities 有权
标题翻译：为存储器控制器提供存储器访问请求合并功能的系统和方法
公开(公告)号：US09032162B1
公开(公告)日：2015-05-12
申请号：US13209137
申请日：2011-08-12
申请人： Ching-Chi Chang , Ravish Kapasi , Jeffrey Schulz , Michael H. M. Chu , Caroline Ssu-Min Chen , Chiakang Sung
发明人： Ching-Chi Chang , Ravish Kapasi , Jeffrey Schulz , Michael H. M. Chu , Caroline Ssu-Min Chen , Chiakang Sung
IPC分类号： G11C7/10
CPC分类号： G11C7/1075 , G06F13/161
摘要： An integrated circuit may include a memory controller serving as an interface between master processing modules and system memory. The master processing modules may provide memory access requests to the memory controller along with respective tag identifications. The memory controller may place the memory access requests in a queue for fulfillment. The memory controller may include a merging module that generates a memory access request to replace two or more memory access requests previously received from the master processing modules. The merging module may store information associated with the memory access requests that were merged and use the stored information to assign appropriate tag identifications to portions of data obtained from system memory when fulfilling the generated memory access request. The memory controller may include a verification module that can be used with test equipment to optimize the design of the master processing modules for improved memory access performance.
摘要翻译：集成电路可以包括用作主处理模块和系统存储器之间的接口的存储器控制器。主处理模块可以向存储器控制器提供存储器访问请求以及相应的标签标识。存储器控制器可以将存储器访问请求放置在队列中以实现。存储器控制器可以包括合并模块，其生成存储器访问请求以替换先前从主处理模块接收的两个或多个存储器访问请求。合并模块可以存储与被合并的存储器访问请求相关联的信息，并使用所存储的信息，以在满足生成的存储器访问请求时从系统存储器获得的数据部分分配适当的标签标识。存储器控制器可以包括可与测试设备一起使用的验证模块，以优化主处理模块的设计以改善存储器访问性能。

3. 发明授权

US09208109B2 Memory controllers with dynamic port priority assignment capabilities 有权
标题翻译：具有动态端口优先级分配功能的内存控制器
公开(公告)号：US09208109B2
公开(公告)日：2015-12-08
申请号：US13151101
申请日：2011-06-01
申请人： Michael H. M. Chu , Jeffrey Schulz , Chiakang Sung , Ravish Kapasi
发明人： Michael H. M. Chu , Jeffrey Schulz , Chiakang Sung , Ravish Kapasi
IPC分类号： G06F12/08 , G06F13/16 , G06F13/18
CPC分类号： G06F13/1626 , G06F13/16 , G06F13/1605 , G06F13/18
摘要： A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have associated priority values and fulfill the memory access requests by configuring system memory to respond to the memory access requests. To dynamically modify the associated priority values while the memory controller receives and fulfills the memory access requests, a priority value update module may be provided that dynamically updates priority values for the memory controller ports. The priority value update module may provide the updated priority values with update registers that are updated based on an update signal and a system clock. The priority values may be provided by shift registers, memory mapped registers, or provided by masters along with each memory access request.
摘要翻译：可编程集成电路可以具有在主模块和系统存储器之间进行接口的存储器控制器。存储器控制器可以通过具有相关优先级值的端口从主设备接收存储器访问请求，并通过配置系统存储器来响应存储器访问请求来满足存储器访问请求。为了在存储器控制器接收并满足存储器访问请求的同时动态地修改相关联的优先级值，可以提供动态地更新存储器控制器端口的优先级值的优先级值更新模块。优先级值更新模块可以根据更新信号和系统时钟向更新的优先级值提供更新的更新寄存器。优先级值可以由移位寄存器，存储器映射寄存器提供，或由主器件与每个存储器访问请求一起提供。

4. 发明授权

US07330051B1 Innovated technique to reduce memory interface write mode SSN in FPGA 有权
标题翻译：在FPGA中减少存储器接口写模式SSN的创新技术
公开(公告)号：US07330051B1
公开(公告)日：2008-02-12
申请号：US11354766
申请日：2006-02-14
申请人： Joseph Huang , Chiakang Sung , Michael H. M. Chu , Yan Chong
发明人： Joseph Huang , Chiakang Sung , Michael H. M. Chu , Yan Chong
IPC分类号： H03K19/173
CPC分类号： H03K19/17744
摘要： The amount of simultaneous switching noise generated through the operation of a programmable device can be reduced by reducing the number of pins switching at the same time. An I/O bank can include a number of I/O pin subsets, or DQS groups, each programmed to switch at a different time so that the switching times of the various pins can be staggered for each system clock cycle. Programmable delay elements can be used to control the delay of each subset. The programmable elements can be placed between the system clock and the output registers in order to delay the receiving of the clock signal by the registers and therefore delaying the switching of the output buffers. The programmable delay elements also can be placed between the output registers and the output buffers in order to delay the receiving of the output data by, and subsequent switching of, the output buffers.
摘要翻译：通过可编程器件的操作产生的同时开关噪声的量可以通过减少引脚数目同时减少。 I / O bank可以包括多个I / O引脚子集或DQS组，每组都被编程为在不同的时间切换，使得各个引脚的切换时间可以在每个系统时钟周期内交错。可编程延迟元件可用于控制每个子集的延迟。可编程元件可以放置在系统时钟和输出寄存器之间，以便延迟寄存器对时钟信号的接收，从而延迟输出缓冲器的切换。可编程延迟元件也可以放置在输出寄存器和输出缓冲器之间，以便延迟输出缓冲器的输出数据的接收和随后的切换。

5. 发明授权

US07492185B1 Innovated technique to reduce memory interface write mode SSN in FPGA 有权
标题翻译：在FPGA中减少存储器接口写模式SSN的创新技术
公开(公告)号：US07492185B1
公开(公告)日：2009-02-17
申请号：US11956182
申请日：2007-12-13
申请人： Joseph Huang , Chiakang Sung , Michael H. M. Chu , Yan Chong
发明人： Joseph Huang , Chiakang Sung , Michael H. M. Chu , Yan Chong
IPC分类号： H03K19/173
CPC分类号： H03K19/17744
摘要： The amount of simultaneous switching noise generated through the operation of a programmable device can be reduced by reducing the number of pins switching at the same time. An I/O bank can include a number of I/O pin subsets, or DQS groups, each programmed to switch at a different time so that the switching times of the various pins can be staggered for each system clock cycle. Programmable delay elements can be used to control the delay of each subset. The programmable elements can be placed between the system clock and the output registers in order to delay the receiving of the clock signal by the registers and therefore delaying the switching of the output buffers. The programmable delay elements also can be placed between the output registers and the output buffers in order to delay the receiving of the output data by, and subsequent switching of, the output buffers.
摘要翻译：通过可编程器件的操作产生的同时开关噪声的量可以通过减少引脚数目同时减少。 I / O bank可以包括多个I / O引脚子集或DQS组，每组都被编程为在不同的时间切换，使得各个引脚的切换时间可以在每个系统时钟周期内交错。可编程延迟元件可用于控制每个子集的延迟。可编程元件可以放置在系统时钟和输出寄存器之间，以便延迟寄存器对时钟信号的接收，从而延迟输出缓冲器的切换。可编程延迟元件也可以放置在输出寄存器和输出缓冲器之间，以便延迟输出缓冲器的输出数据的接收和随后的切换。

6. 发明授权

US07593273B2 Read-leveling implementations for DDR3 applications on an FPGA 有权
标题翻译： FPGA上DDR3应用程序的读取级别实现
公开(公告)号：US07593273B2
公开(公告)日：2009-09-22
申请号：US11935310
申请日：2007-11-05
申请人： Michael H. M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
发明人： Michael H. M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , H03L7/06 , H03L7/0812
摘要： Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.
摘要翻译：用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。一个例子是通过在输入和电路之间使用重新定时元件实现这一点。重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。平均接收无差错数据的最小和最大延迟。然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。在一个示例中，输入信号可以被延迟与延迟设置相对应的量。在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。

7. 发明授权

US07589556B1 Dynamic control of memory interface timing 有权
标题翻译：动态控制存储器接口时序
公开(公告)号：US07589556B1
公开(公告)日：2009-09-15
申请号：US11925717
申请日：2007-10-26
申请人： Johnson Tan , Andrew Bellis , Philip Clarke , Yan Chong , Joseph Huang , Michael H. M. Chu , Chiakang Sung
发明人： Johnson Tan , Andrew Bellis , Philip Clarke , Yan Chong , Joseph Huang , Michael H. M. Chu , Chiakang Sung
IPC分类号： G06F7/38
CPC分类号： H03M9/00 , H03K5/131 , H03K5/133 , H03K5/135 , H03K2005/00058
摘要： Circuits, methods, and apparatus for the dynamic control of calibration data that adjusts the timing of input and output signals on an integrated circuit. This dynamic control allows input and output circuits to self-calibrate by compensating for temperature and voltage changes in an efficient manner, without the need for device reconfiguration. Calibration settings can be maintained while new calibration settings are loaded. Skew between clock and data signals, as well as among multiple data signals, can be reduced. Dynamic control is achieved while consuming only a minimal resources including route paths.
摘要翻译：用于动态控制校准数据的电路，方法和装置，用于调整集成电路上的输入和输出信号的时序。该动态控制允许输入和输出电路通过以有效的方式补偿温度和电压变化而进行自校准，而不需要对器件重新配置。加载新的校准设置时，可以保持校准设置。可以减少时钟和数据信号之间以及多个数据信号之间的偏移。实现动态控制，同时仅消耗包括路由路径在内的最小资源。

8. 发明授权

US08671303B2 Write-leveling implementation in programmable logic devices 有权
标题翻译：在可编程逻辑器件中编写调平实现
公开(公告)号：US08671303B2
公开(公告)日：2014-03-11
申请号：US13349228
申请日：2012-01-12
申请人： Yan Chong , Bonnie I. Wang , Chiakang Sung , Joseph Huang , Michael H. M. Chu
发明人： Yan Chong , Bonnie I. Wang , Chiakang Sung , Joseph Huang , Michael H. M. Chu
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/222
摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.
摘要翻译：用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。在一个示例性校准例程中，向接收设备提供时钟信号。还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

9. 发明授权

US08122275B2 Write-leveling implementation in programmable logic devices 有权
标题翻译：在可编程逻辑器件中编写调平实现
公开(公告)号：US08122275B2
公开(公告)日：2012-02-21
申请号：US11843123
申请日：2007-08-22
申请人： Yan Chong , Bonnie I. Wang , Chiakang Sung , Joseph Huang , Michael H. M. Chu
发明人： Yan Chong , Bonnie I. Wang , Chiakang Sung , Joseph Huang , Michael H. M. Chu
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/222
摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.
摘要翻译：用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。在一个示例性校准例程中，向接收设备提供时钟信号。还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

10. 发明授权

US07990786B2 Read-leveling implementations for DDR3 applications on an FPGA 有权
标题翻译： FPGA上DDR3应用程序的读取级别实现
公开(公告)号：US07990786B2
公开(公告)日：2011-08-02
申请号：US12539582
申请日：2009-08-11
申请人： Michael H. M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
发明人： Michael H. M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , H03L7/06 , H03L7/0812
摘要： Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.
摘要翻译：用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。一个例子是通过在输入和电路之间使用重新定时元件实现这一点。重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。平均接收无差错数据的最小和最大延迟。然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。在一个示例中，输入信号可以被延迟与延迟设置相对应的量。在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。

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