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    • 4. 发明申请
    • Method and apparatus for solid-state microbattery photolithographic manufacture, singulation and passivation
    • 固态微电池光刻制造,单片化和钝化的方法和装置
    • US20080032236A1
    • 2008-02-07
    • US11879745
    • 2007-07-18
    • Mark WallaceJody KlaassenJeffrey SatherStuart Shakespeare
    • Mark WallaceJody KlaassenJeffrey SatherStuart Shakespeare
    • H01M10/04C23F1/00
    • H01M10/045H01M4/525H01M6/40H01M10/04H01M10/0436H01M10/052H01M10/056H01M10/0562H01M10/0585H01M2010/0495H01M2300/0094
    • A method for producing a thin film lithium battery is provided, comprising applying a cathode current collector, a cathode material, an anode current collector, and an electrolyte layer separating the cathode material from the anode current collector to a substrate, wherein at least one of the layers contains lithiated compounds that is patterned at least in part by a photolithography operation comprising removal of a photoresist material from the layer containing lithiated compounds by a process including a wet chemical treatment. Additionally, a method and apparatus for making lithium batteries by providing a first sheet that includes a substrate having a cathode material, an anode material, and a LiPON barrier/electrolyte layer separating the cathode material from the anode material; and removing a subset of first material to separate a plurality of cells from the first sheet. In some embodiments, the method further includes depositing second material on the sheet to cover the plurality of cells; and removing a subset of second material to separate a plurality of cells from the first sheet.
    • 本发明提供一种薄膜锂电池的制造方法,其特征在于,在正极集电体,阴极材料,阳极集电体以及将阴极材料与阳极集电体分离成基板的电解质层的基础上, 该层包含至少部分通过光刻操作图案化的锂化化合物,其包括通过包括湿化学处理的方法从含有锂化合物的层除去光致抗蚀剂材料。 另外,提供一种第一片材制造锂电池的方法和装置,所述第一片材包括具有阴极材料的衬底,阳极材料和将阳极材料与阳极材料分离的LiPON阻挡/电解质层; 以及去除第一材料的子集以将多个细胞与第一片材分离。 在一些实施例中,该方法还包括在片材上沉积第二材料以覆盖多个细胞; 以及移除第二材料的子集以从所述第一片分离多个细胞。
    • 5. 发明授权
    • Method and system for area efficient charge-based capacitance measurement
    • 用于区域高效充电电容测量的方法和系统
    • US07106073B1
    • 2006-09-12
    • US11140142
    • 2005-05-27
    • Randall BachJeffrey Sather
    • Randall BachJeffrey Sather
    • G01R27/26
    • G01R31/2884G01R31/2856
    • The present invention is directed to a system for area efficient charge-based capacitance measurement requiring a minimum silicon area for probe pads. A structure block for the system includes several test structures coupled to a target test capacitance structure, a reference structure, and a logic block. Each test structure is coupled to a corresponding test capacitance structure. The logic block coupled to the several test structures selects a desirable test structure from the several test structures. The system may include several structure blocks and an additional logic block to select a desirable structure block. Each structure block includes a single output pin for busing each test output from the several test structures. In this manner, the silicon area may be minimized through reduction of the number of total pins and probe pads required.
    • 本发明涉及一种用于区域高效的基于电荷的电容测量的系统,其需要用于探针焊盘的最小硅面积。 该系统的结构块包括耦合到目标测试电容结构,参考结构和逻辑块的若干测试结构。 每个测试结构耦合到相应的测试电容结构。 耦合到若干测试结构的逻辑块从几个测试结构中选择期望的测试结构。 该系统可以包括几个结构块和用于选择期望的结构块的附加逻辑块。 每个结构块包括一个单个输出引脚,用于引导来自多个测试结构的每个测试输出。 以这种方式,可以通过减少所需的总引脚和探针焊盘的数量来最小化硅面积。