专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08196086B2 Granular channel width for power optimization 有权
标题翻译：颗粒通道宽度进行功率优化
公开(公告)号：US08196086B2
公开(公告)日：2012-06-05
申请号：US12840535
申请日：2010-07-21
申请人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
发明人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/78
摘要： A storage medium recording a cell library having one or more cells that may be readable by a computer and may be used by the computer to design an integrated circuit. The one or more cells may have a physical dimension parameter and a channel width parameter. The physical dimension parameter may be a footprint of the one or more cells. The channel width parameter may have a minimum driver size and a maximum driver size. The channel width parameter may define a range within which a tool varies the channel width between the maximum driver size and the minimum driver size during a design flow of the integrated circuit based upon one or more power criteria without changing the footprint.
摘要翻译：记录具有一个或多个可由计算机读取的单元的单元库的存储介质，并可由计算机用于设计集成电路。一个或多个单元可以具有物理尺寸参数和通道宽度参数。物理尺寸参数可以是一个或多个单元格的占位面积。通道宽度参数可能具有最小驱动程序大小和最大驱动程序大小。通道宽度参数可以定义范围，在该范围内，工具在集成电路的设计流程期间基于一个或多个功率准则改变最大驱动器尺寸和最小驱动器尺寸之间的通道宽度，而不改变占用面积。

2. 发明授权

US07966592B2 Dual path static timing analysis 有权
标题翻译：双路静态时序分析
公开(公告)号：US07966592B2
公开(公告)日：2011-06-21
申请号：US12206048
申请日：2008-09-08
申请人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
发明人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method to analyze timing in a circuit, generally including (A) simulating reception of an input signal and a clock signal at a first flip-flop, wherein (i) the input signal has a latest transition, (ii) the input signal arrives through a first path and (iii) the clock signal has an active edge, (B) calculating a value of a time difference between the latest transition and the active edge, (C) calculating a delay between the active edge and the latest transition appearing in an output signal, wherein (i) the delay is based on a model responding to the value, (ii) the model characterizes a clock-to-output delay as a function of the time difference and (iii) the characterization covering a range of values, (D) calculating an arrival time of the latest transition at a second flip-flop through a second signal path and (E) storing the arrival time in a recording medium.
摘要翻译：一种分析电路中的定时的方法，通常包括（A）模拟第一触发器处的输入信号和时钟信号的接收，其中（i）输入信号具有最新的转换，（ii）输入信号到达通过第一路径和（iii）时钟信号具有有效边缘，（B）计算最新转换和有效边沿之间的时间差值，（C）计算出当前边缘与最近转换出现之间的延迟在输出信号中，其中（i）所述延迟基于响应于该值的模型，（ii）模型将时钟到输出延迟表征为时间差的函数，以及（iii）表征范围（D）通过第二信号路径计算第二触发器的最新转换的到达时间，以及（E）将到达时间存储在记录介质中。

3. 发明授权

US07787325B2 Row decode driver gradient design in a memory device 有权
标题翻译：行解码驱动程序渐变设计在内存设备中
公开(公告)号：US07787325B2
公开(公告)日：2010-08-31
申请号：US12120611
申请日：2008-05-14
申请人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
发明人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： A memory device using a plurality of enhanced row decode drivers for activating wordlines in a memory array is disclosed. Circuit design attributes of the enhanced row decode drivers are varied as a function of proximity to a source of a row address signal applied to each decode driver. The circuit variations are operable to reduce the leakage power of the driver by degrading performance thereof while maintaining required worst case timing. The worst case timing being defined by the timing and performance requirements for the most distant of the row decode driver circuits relative to the source of the applied row address signals.
摘要翻译：公开了一种使用多个用于激活存储器阵列中的字线的增强行解码驱动器的存储器件。增强行解码驱动器的电路设计属性作为与施加到每个解码驱动器的行地址信号的源的接近度的函数而变化。电路变化可操作以通过降低其性能而降低驾驶员的泄漏功率，同时保持所需的最差情况时机。最差的情况定时由相对于应用的行地址信号的源的最远的行解码驱动器电路的定时和性能要求定义。

4. 发明授权

US08336018B2 Power grid optimization 失效
标题翻译：电网优化
公开(公告)号：US08336018B2
公开(公告)日：2012-12-18
申请号：US12796906
申请日：2010-06-09
申请人： Mark F. Turner , Jonathan W. Byrn , Jeffrey S. Brown
发明人： Mark F. Turner , Jonathan W. Byrn , Jeffrey S. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/78 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A global power distribution network in an integrated circuit comprising a first layer of conductive material and a second layer of conductive material. The first layer of conductive material may be (i) coupled to one or more power supplies and (ii) configured to form a plurality of first rails of a mesh. The first rails may (a) supply power to one or more components of a core logic of the integrated circuit, (b) be aligned with a first axis of the integrated circuit, and (c) have one or more parameters configured such that the mesh has a uniform voltage gradient from a perimeter of the integrated circuit to a center of the integrated circuit along the first axis. The second layer of conductive material may be (i) coupled to the one or more power supplies and (ii) configured to form a plurality of second rails of the mesh. The second rails may (a) supply power to one or more components of the core logic, (b) be aligned with a second axis of the integrated circuit, and (c) have one or more parameters configured such that the mesh comprises a uniform voltage gradient from the perimeter of the integrated circuit to the center of the integrated circuit along the second axis.
摘要翻译：一种集成电路中的全球配电网络，包括第一导电材料层和第二导电材料层。第一层导电材料可以是（i）耦合到一个或多个电源，并且（ii）被配置成形成多个网格的第一轨道。第一轨道可以（a）向集成电路的核心逻辑的一个或多个部件供电，（b）与集成电路的第一轴对准，以及（c）具有一个或多个参数，网格具有从集成电路的周边到沿着第一轴的集成电路的中心的均匀的电压梯度。第二层导电材料可以是（i）耦合到一个或多个电源，并且（ii）被配置成形成网状物的多个第二轨道。第二轨道可以（a）向核心逻辑器件的一个或多个部件供电，（b）与集成电路的第二轴对齐，并且（c）具有一个或多个参数，使得该网格包括均匀的从集成电路的周边到沿着第二轴的集成电路的中心的电压梯度。

5. 发明申请

US20110304052A1 POWER GRID OPTIMIZATION 失效
标题翻译：电网优化
公开(公告)号：US20110304052A1
公开(公告)日：2011-12-15
申请号：US12796906
申请日：2010-06-09
申请人： Mark F. Turner , Jonathan W. Byrn , Jeffrey S. Brown
发明人： Mark F. Turner , Jonathan W. Byrn , Jeffrey S. Brown
IPC分类号： H01L23/50 , G06F17/50
CPC分类号： G06F17/5077 , G06F2217/78 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A global power distribution network in an integrated circuit comprising a first layer of conductive material and a second layer of conductive material. The first layer of conductive material may be (i) coupled to one or more power supplies and (ii) configured to form a plurality of first rails of a mesh. The first rails may (a) supply power to one or more components of a core logic of the integrated circuit, (b) be aligned with a first axis of the integrated circuit, and (c) have one or more parameters configured such that the mesh has a uniform voltage gradient from a perimeter of the integrated circuit to a center of the integrated circuit along the first axis. The second layer of conductive material may be (i) coupled to the one or more power supplies and (ii) configured to form a plurality of second rails of the mesh. The second rails may (a) supply power to one or more components of the core logic, (b) be aligned with a second axis of the integrated circuit, and (c) have one or more parameters configured such that the mesh comprises a uniform voltage gradient from the perimeter of the integrated circuit to the center of the integrated circuit along the second axis.
摘要翻译：一种集成电路中的全球配电网络，包括第一导电材料层和第二导电材料层。第一层导电材料可以是（i）耦合到一个或多个电源，并且（ii）被配置成形成多个网格的第一轨道。第一轨道可以（a）向集成电路的核心逻辑的一个或多个部件供电，（b）与集成电路的第一轴对准，以及（c）具有一个或多个参数，网格具有从集成电路的周边到沿着第一轴的集成电路的中心的均匀的电压梯度。第二层导电材料可以是（i）耦合到一个或多个电源，并且（ii）被配置成形成网状物的多个第二轨道。第二轨道可以（a）向核心逻辑器件的一个或多个部件供电，（b）与集成电路的第二轴对齐，并且（c）具有一个或多个参数，使得该网格包括均匀的从集成电路的周边到沿着第二轴的集成电路的中心的电压梯度。

6. 发明申请

US20090164956A1 REDISTRIBUTION OF CURRENT DEMAND AND REDUCTION OF POWER AND DCAP 有权
标题翻译：重新分配电流需求和减少功率和DCAP
公开(公告)号：US20090164956A1
公开(公告)日：2009-06-25
申请号：US11962165
申请日：2007-12-21
申请人： Jonathan W. Byrn , Mark F. Turner , Jeffrey S. Brown
发明人： Jonathan W. Byrn , Mark F. Turner , Jeffrey S. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method to redistribute current demand is presented. The method includes a first step of determining timing arc data for one or more timing arcs of a circuit design. The method includes a second step of checking the timing arc data for delay shift target cells. The method includes a further step of swapping a delay shift target cell with a delay shift cell.
摘要翻译：介绍了一种重新分配当前需求的方法。该方法包括确定电路设计的一个或多个定时弧的定时弧数据的第一步骤。该方法包括检查用于延迟移位目标小区的定时弧数据的第二步骤。该方法还包括用延迟移位单元交换延迟移位目标小区的另一步骤。

7. 发明申请

US20080244474A1 Cell library management for power optimization 失效
标题翻译：电池库管理功率优化
公开(公告)号：US20080244474A1
公开(公告)日：2008-10-02
申请号：US11732092
申请日：2007-04-02
申请人： Mark F. Turner , Jonathan W. Byrn , Jeffrey S. Brown
发明人： Mark F. Turner , Jonathan W. Byrn , Jeffrey S. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method of managing a cell library regarding power optimization is disclosed. The method generally includes the steps of (A) reading a plurality of first modules within a first region of a circuit design stored in a design file, (B) calculating a first merit value indicating a relative sensitivity of the first region to a power consumption, the first merit value having a range from a static power dominated value to a dynamic power dominated value and (C) creating a constraint file configured to limit a design tool to a first subset of a plurality of replacement modules based on the first merit value such that the design tool automatically optimizes the power consumption of the first region by replacing at least one of the first modules with at least one of the replacement modules within the first subset, the replacement modules residing in a library file.
摘要翻译：公开了一种管理关于功率优化的单元库的方法。该方法通常包括以下步骤：（A）读取存储在设计文件中的电路设计的第一区域内的多个第一模块，（B）计算指示第一区域相对于功耗的相对灵敏度的第一优值值所述第一优点值具有从静态功率主导值到动态功率主导值的范围，以及（C）创建约束文件，其被配置为基于所述第一优点值将设计工具限制到多个替换模块的第一子集使得设计工具通过用第一子集内的至少一个替换模块替换至少一个第一模块来自动优化第一区域的功耗，所述替换模块驻留在库文件中。

8. 发明申请

US20120023473A1 GRANULAR CHANNEL WIDTH FOR POWER OPTIMIZATION 有权
标题翻译：用于功率优化的颗粒通道宽度
公开(公告)号：US20120023473A1
公开(公告)日：2012-01-26
申请号：US12840535
申请日：2010-07-21
申请人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
发明人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/78
摘要： A storage medium recording a cell library having one or more cells that may be readable by a computer and may be used by the computer to design an integrated circuit. The one or more cells may have a physical dimension parameter and a channel width parameter. The physical dimension parameter may be a footprint of the one or more cells. The channel width parameter may have a minimum driver size and a maximum driver size. The channel width parameter may define a range within which a tool varies the channel width between the maximum driver size and the minimum driver size during a design flow of the integrated circuit based upon one or more power criteria without changing the footprint.
摘要翻译：记录具有一个或多个可由计算机读取的单元的单元库的存储介质，并可由计算机用于设计集成电路。一个或多个单元可以具有物理尺寸参数和通道宽度参数。物理尺寸参数可以是一个或多个单元格的占位面积。通道宽度参数可能具有最小驱动程序大小和最大驱动程序大小。通道宽度参数可以定义范围，在该范围内，工具在集成电路的设计流程期间基于一个或多个功率准则改变最大驱动器尺寸和最小驱动器尺寸之间的通道宽度，而不改变占用面积。

9. 发明授权

US07818695B2 Redistribution of current demand and reduction of power and DCAP 有权
标题翻译：当前需求的再分配和电力的减少和DCAP
公开(公告)号：US07818695B2
公开(公告)日：2010-10-19
申请号：US11962165
申请日：2007-12-21
申请人： Jonathan W. Byrn , Mark F. Turner , Jeffrey S. Brown
发明人： Jonathan W. Byrn , Mark F. Turner , Jeffrey S. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method to redistribute current demand is presented. The method includes a first step of determining timing arc data for one or more timing arcs of a circuit design. The method includes a second step of checking the timing arc data for delay shift target cells. The method includes a further step of swapping a delay shift target cell with a delay shift cell.
摘要翻译：介绍了一种重新分配当前需求的方法。该方法包括确定电路设计的一个或多个定时弧的定时弧数据的第一步骤。该方法包括检查用于延迟移位目标小区的定时弧数据的第二步骤。该方法还包括用延迟移位单元交换延迟移位目标小区的另一步骤。

10. 发明申请

US20090285047A1 ROW DECODE DRIVER GRADIENT DESIGN IN A MEMORY DEVICE 有权
标题翻译： ROW解码驱动器等级设计在存储器件中
公开(公告)号：US20090285047A1
公开(公告)日：2009-11-19
申请号：US12120611
申请日：2008-05-14
申请人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
发明人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
IPC分类号： G11C8/08
CPC分类号： G11C8/10
摘要： A memory device using a plurality of enhanced row decode drivers for activating wordlines in a memory array is disclosed. Circuit design attributes of the enhanced row decode drivers are varied as a function of proximity to a source of a row address signal applied to each decode driver. The circuit variations are operable to reduce the leakage power of the driver by degrading performance thereof while maintaining required worst case timing. The worst case timing being defined by the timing and performance requirements for the most distant of the row decode driver circuits relative to the source of the applied row address signals.
摘要翻译：公开了一种使用多个用于激活存储器阵列中的字线的增强行解码驱动器的存储器件。增强行解码驱动器的电路设计属性作为与施加到每个解码驱动器的行地址信号的源的接近度的函数而变化。电路变化可操作以通过降低其性能而降低驾驶员的泄漏功率，同时保持所需的最差情况时机。最差的情况定时由相对于应用的行地址信号的源的最远的行解码驱动器电路的定时和性能要求定义。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式