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1. 发明授权

US07315952B2 Power state coordination between devices sharing power-managed resources 有权
标题翻译：共享权力管理资源的设备之间的电源状态协调
公开(公告)号：US07315952B2
公开(公告)日：2008-01-01
申请号：US10871638
申请日：2004-06-17
申请人： Jeffrey R. Wilcox , Shivnandan Kaushik , Stephen H. Gunther , Devadatta V. Bodas , Siva Ramakrishnan , David Poisner , Lance E. Hacking
发明人： Jeffrey R. Wilcox , Shivnandan Kaushik , Stephen H. Gunther , Devadatta V. Bodas , Siva Ramakrishnan , David Poisner , Lance E. Hacking
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3246 , G06F1/3287 , Y02D10/171 , Y10T307/438
摘要： Methods and apparatuses for coordination of power state management in and electronic system.
摘要翻译：电力系统管理与电力系统协调的方法与装置。

2. 发明授权

US07272741B2 Hardware coordination of power management activities 有权
标题翻译：电力管理活动的硬件协调
公开(公告)号：US07272741B2
公开(公告)日：2007-09-18
申请号：US10859892
申请日：2004-06-02
申请人： Jeffrey R. Wilcox , Shivnandan Kaushik , Stephen H. Gunther , Devadatta V. Bodas , Siva Ramakrishnan , David Poisner , Bernard J. Lint , Lance E. Hacking
发明人： Jeffrey R. Wilcox , Shivnandan Kaushik , Stephen H. Gunther , Devadatta V. Bodas , Siva Ramakrishnan , David Poisner , Bernard J. Lint , Lance E. Hacking
IPC分类号： G06F1/08
CPC分类号： G06F1/3203
摘要： Systems and methods of managing power provide for receiving notification of a pending power state transition and using coordination hardware to determine whether the power state transition in a primary device is permitted by a set of secondary devices. In one embodiment, the primary device shares a resource with the set of secondary devices.
摘要翻译：管理电力的系统和方法提供接收待决功率状态转换的通知并使用协调硬件来确定主设备中的电力状态转换是否被一组辅助设备所允许。在一个实施例中，主设备与该组次级设备共享资源。

3. 发明授权

US07360103B2 P-state feedback to operating system with hardware coordination 有权
标题翻译： P状态反馈到操作系统与硬件协调
公开(公告)号：US07360103B2
公开(公告)日：2008-04-15
申请号：US10850775
申请日：2004-05-21
申请人： Bernard J. Lint , Alon Naveh , Shivnandan D. Kaushik , Jeffrey R. Wilcox , Lance E. Hacking , Ping Sager , Kushagra Vaid , Todd A. Dutton
发明人： Bernard J. Lint , Alon Naveh , Shivnandan D. Kaushik , Jeffrey R. Wilcox , Lance E. Hacking , Ping Sager , Kushagra Vaid , Todd A. Dutton
IPC分类号： G06F1/00 , G06F3/00
CPC分类号： G06F11/3419 , G06F11/3452 , G06F11/3466 , G06F2201/88 , Y02D10/34
摘要： A mechanism for P-state feedback to operating system (OS) with hardware coordination is described herein. In one embodiment, an example of a process includes, but is not limited to, receiving data from a processor representing an average performance over a previous period of time, and determining a performance state (P-state) for a next period of time based in part on the data representing the average performance over the previous period of time. Other methods and apparatuses are also described.
摘要翻译：这里描述了具有硬件协调的用于P状态反馈到操作系统（OS）的机制。在一个实施例中，过程的示例包括但不限于从处理器接收表示在先前时间段内的平均性能的数据，以及基于下一个时间段确定性能状态（P状态）部分来自表示前一段时间内的平均表现的数据。还描述了其它方法和装置。

4. 发明授权

US08656411B2 Technique for monitoring activity within an integrated circuit 有权
标题翻译：集成电路内监控活动的技术
公开(公告)号：US08656411B2
公开(公告)日：2014-02-18
申请号：US12042992
申请日：2008-03-05
申请人： Lance E. Hacking
发明人： Lance E. Hacking
IPC分类号： G06F9/44 , G06F9/46
CPC分类号： G06F9/542 , G06F11/30 , G06F11/3466 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A technique to monitor events within a computer system or integrated circuit. In one embodiment, a software-accessible event monitoring storage and hardware-specific monitoring logic are selectable and their corresponding outputs may be monitored by accessing a counter to count events corresponding to each of software-accessible storage and hardware-specific monitoring logic.
摘要翻译：监控计算机系统或集成电路中的事件的技术。在一个实施例中，可以选择软件可访问事件监视存储和硬件特定的监视逻辑，并且可以通过访问计数器来监视其对应的输出，以计数与软件可访问的存储和硬件特定的监视逻辑中的每一个对应的事件。

5. 发明申请

US20100332686A1 WRITE COMBINING PROTOCOL BETWEEN PROCESSORS AND CHIPSETS 有权
标题翻译：处理器和芯片之间的写组合协议
公开(公告)号：US20100332686A1
公开(公告)日：2010-12-30
申请号：US12689899
申请日：2010-01-19
申请人： Kenneth C. Creta , Aaron T. Spink , Lance E. Hacking , Sridhar Muthrasanallur , Jasmin Ajanovic
发明人： Kenneth C. Creta , Aaron T. Spink , Lance E. Hacking , Sridhar Muthrasanallur , Jasmin Ajanovic
IPC分类号： G06F3/00 , G06F12/08 , G06F5/00
CPC分类号： G06F13/4027
摘要： Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.
摘要翻译：处理写事务的系统和方法提供了根据I / O集线器和处理器之间的协议在输入/输出（I / O）集线器上组合写事务。与写入事务相关的数据可以刷新到I / O设备，而不需要I / O设备内的专有软件和专用寄存器。

6. 发明授权

US07676603B2 Write combining protocol between processors and chipsets 失效
标题翻译：在处理器和芯片组之间写入组合协议
公开(公告)号：US07676603B2
公开(公告)日：2010-03-09
申请号：US10828872
申请日：2004-04-20
申请人： Kenneth C. Creta , Aaron T. Spink , Lance E. Hacking , Sridhar Muthrasanallur , Jasmin Ajanovic
发明人： Kenneth C. Creta , Aaron T. Spink , Lance E. Hacking , Sridhar Muthrasanallur , Jasmin Ajanovic
IPC分类号： G06F3/00
CPC分类号： G06F13/4027
摘要： Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.
摘要翻译：处理写事务的系统和方法提供了根据I / O集线器和处理器之间的协议在输入/输出（I / O）集线器上组合写事务。与写入事务相关的数据可以刷新到I / O设备，而不需要I / O设备内的专有软件和专用寄存器。

7. 发明授权

US07249245B2 Globally observing load operations prior to fence instruction and post-serialization modes 有权
标题翻译：在栅栏指令和后序列化模式之前，全局观察加载操作
公开(公告)号：US07249245B2
公开(公告)日：2007-07-24
申请号：US10778512
申请日：2004-02-12
申请人： Lance E. Hacking , Debbie Marr
发明人： Lance E. Hacking , Debbie Marr
IPC分类号： G06F9/312
CPC分类号： G06F9/30087 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A system includes a memory unit and a processor where the processor has a load buffer to store a first instruction and a cache controller to block the first instruction from dispatch into the cache controller until load data for load operations prior to the first instruction fetched from the memory unit are globally observed. The processor further may include a control register having a first mode storage to store a mode control selection for pre-serialization and a second mode storage to store a mode control selection for post-serialization to enable control of pre-serialization and post-serialization of load operations with respect to the first instruction. Other embodiments are described and claimed.
摘要翻译：一种系统包括存储器单元和处理器，其中处理器具有负载缓冲器以存储第一指令和高速缓存控制器，以将第一指令阻止到高速缓存控制器的调度中，直到在从第一指令取出第一指令之前的加载操作的加载数据全局观察记忆单元。处理器还可以包括具有第一模式存储器的控制寄存器，用于存储用于预序列化的模式控制选择，以及存储用于后序列化的模式控制选择的第二模式存储，以使得能够控制前序列化和后序列化相对于第一条指令的加载操作。描述和要求保护其他实施例。

8. 发明授权

US09830954B2 Method and system for dynamic power management of memories 有权
公开(公告)号：US09830954B2
公开(公告)日：2017-11-28
申请号：US13069647
申请日：2011-03-23
申请人： Lance E. Hacking , Hee-Jun Park
发明人： Lance E. Hacking , Hee-Jun Park
IPC分类号： G11C5/14 , G11C11/4074
CPC分类号： G11C5/147 , G11C5/148 , G11C11/4074
摘要： A method and apparatus for dynamic power management of memories. In one embodiment of the invention, the power consumption of the memories is reduced based on the operating state of the memories. For example, in one embodiment of the invention, the power supply to the memories is reduced when the memories are in an inactive state by reducing and/or turning off the input voltage(s) to the memories. In one embodiment of the invention, the processing unit dynamically changes the strength of the On-Die Termination pull-up/pull-down resistance based on the memory operating mode, memory voltage, and memory temperature.

9. 发明授权

US08650629B2 Interface logic for a multi-core system-on-a-chip (SoC) 失效
标题翻译：多核系统芯片（SoC）的接口逻辑
公开(公告)号：US08650629B2
公开(公告)日：2014-02-11
申请号：US12639258
申请日：2009-12-16
申请人： Ramana Rachakonda , Lance E. Hacking , Mahesh K. Reddy , Lori R. Borger , Chee Hak Teh , Pawitter P. Bhatia , John P. Lee
发明人： Ramana Rachakonda , Lance E. Hacking , Mahesh K. Reddy , Lori R. Borger , Chee Hak Teh , Pawitter P. Bhatia , John P. Lee
IPC分类号： G06F21/22
CPC分类号： G06F13/40 , G01R31/318572 , G06F15/7807 , G06F15/7842 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有第一和第二核心的系统级芯片（SoC），耦合到核心的接口逻辑，耦合到接口逻辑的芯片组逻辑以及耦合在芯片组逻辑之间的虚拟防火墙逻辑和第二核心。接口逻辑可以包括防火墙逻辑，总线逻辑和测试逻辑，并且芯片组逻辑可以包括存储器控制器以提供与耦合到SoC的存储器的通信。在一些系统实现中，无论是在测试操作还是功能操作期间，在正常操作期间可以禁用第二个内核以提供单个核心SoC，从而在许多不同实现中使SoC的灵活性更高。描述和要求保护其他实施例。

10. 发明申请

US20110145909A1 Interface Logic For A Multi-Core System-On-A-Chip (SoC) 失效
标题翻译：多核系统芯片（SoC）的接口逻辑
公开(公告)号：US20110145909A1
公开(公告)日：2011-06-16
申请号：US12639258
申请日：2009-12-16
申请人： Ramana Rachakonda , Lance E. Hacking , Mahesh K. Reddy , Lori R. Borger , Chee Hak Teh , Pawitter P. Bhatia , John P. Lee
发明人： Ramana Rachakonda , Lance E. Hacking , Mahesh K. Reddy , Lori R. Borger , Chee Hak Teh , Pawitter P. Bhatia , John P. Lee
IPC分类号： G06F21/22
CPC分类号： G06F13/40 , G01R31/318572 , G06F15/7807 , G06F15/7842 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有第一和第二核心的系统级芯片（SoC），耦合到核心的接口逻辑，耦合到接口逻辑的芯片组逻辑以及耦合在芯片组逻辑之间的虚拟防火墙逻辑和第二核心。接口逻辑可以包括防火墙逻辑，总线逻辑和测试逻辑，并且芯片组逻辑可以包括存储器控制器以提供与耦合到SoC的存储器的通信。在一些系统实现中，无论是在测试操作还是功能操作期间，在正常操作期间可以禁用第二个内核以提供单个核心SoC，从而在许多不同实现中使SoC的灵活性更高。描述和要求保护其他实施例。

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