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1. 发明授权

US5154514A On-chip temperature sensor utilizing a Schottky barrier diode structure 失效
标题翻译：利用肖特基势垒二极管结构的片上温度传感器
公开(公告)号：US5154514A
公开(公告)日：1992-10-13
申请号：US751490
申请日：1991-08-29
申请人： Jeffrey P. Gambino , Louis L. Hsu , Michael A. Lee , Krishna Seshan , Alvin Sugerman , Francis E. Turene
发明人： Jeffrey P. Gambino , Louis L. Hsu , Michael A. Lee , Krishna Seshan , Alvin Sugerman , Francis E. Turene
IPC分类号： G01K7/01
CPC分类号： G01K7/01
摘要： A temperature sensor, comprising: a diode structure including, a) a silicon substrate, b) a first region of a metal silicide in the silicon substrate, c) a second region of a metal-oxide semiconductor material on the first region, d) a third region of a metal over the second region; and, means for using the diode structure as a temperature sensitive device to measure an ambient temperature. The metal-oxide semiconductor material is preferably selected to have a bandgap of not less than about 3.0 eV.
摘要翻译： 1.一种温度传感器，包括：二极管结构，包括：a）硅衬底，b）所述硅衬底中的金属硅化物的第一区域，c）所述第一区域上的金属氧化物半导体材料的第二区域，d）第二区域上的金属的第三区域; 以及用于使用二极管结构作为温度敏感设备来测量环境温度的装置。金属氧化物半导体材料优选选择为具有不小于约3.0eV的带隙。

2. 发明授权

US06873017B2 ESD protection for semiconductor products 失效
标题翻译：半导体产品的ESD保护
公开(公告)号：US06873017B2
公开(公告)日：2005-03-29
申请号：US10438349
申请日：2003-05-14
申请人： Jun Cai , Alvin Sugerman , Steven Park
发明人： Jun Cai , Alvin Sugerman , Steven Park
IPC分类号： H01L20060101 , H01L21/338 , H01L23/62 , H01L27/02 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7833 , H01L27/0266
摘要： Device 60 in FIG. 3 has junctions 86 each with a lateral portion 90 and a second portion 92 extending upward toward the surface 12 from the lateral portion 90. The lateral portions 90, as illustrated in FIG. 3, are more or less formed along a plane parallel with the surface 12. The upwardly extending portions 92 include characteristic curved edges of the diffusion fronts which are associated with the planar process. With the regions 80 and 82 each having relatively high net dopant concentrations of different conductivity types, each lateral junction portion 90 includes a relatively large sub region 96 which extends more deeply into the layer 10. When compared to other portions of the junctions 86, the subregions 96 are characterized by a relatively low breakdown voltage so that ESD current is initially directed vertically rather than laterally.
摘要翻译：图6中的装置60。 3具有各自具有侧面部分90的接合部86和从侧面部分90朝向表面12向上延伸的第二部分92。 3或多或少地沿着与表面12平行的平面形成。向上延伸部分92包括与平面过程相关联的扩散前沿的特征弯曲边缘。每个区域80和82各自具有不同导电类型的相对较高的净掺杂剂浓度，每个横向接合部分90包括更深地延伸到层10中的较大的子区域96.当与接头86的其他部分相比时，子区域96的特征在于相对较低的击穿电压，使得ESD电流最初垂直而不是横向地指向。

3. 发明授权

US06646840B1 Internally triggered electrostatic device clamp with stand-off voltage 失效
标题翻译：内部触发静电装置夹具具有支架电压
公开(公告)号：US06646840B1
公开(公告)日：2003-11-11
申请号：US09630946
申请日：2000-08-03
申请人： Alvin Sugerman , Raymond Roberts , Michael Harley-Stead
发明人： Alvin Sugerman , Raymond Roberts , Michael Harley-Stead
IPC分类号： H02H904
CPC分类号： H01L27/0251
摘要： An ESD protection device including a compound transistor structure having a trigger transistor and an ESD protection transistor. The trigger transistor includes a breakdown potential between the standoff voltage of a circuit to be protected and the breakdown potential of the ESD protection transistor. When activated, the trigger transistor operates to turn on the ESD protection transistor that is designed to carry the bulk of the conduction current associated with an ESD event. The trigger transistor is designed with an internal gain mechanism to ensure that it will not be turned off when a modified snapback voltage is reached during the ESD protection transistor operation. The trigger transistor is a minor contributor to the conducting current with the ESD protection transistor after such time as protection circuit operation acts. A process for fabricating a suitable compound transistor structure is disclosed.
摘要翻译：一种ESD保护装置，包括具有触发晶体管和ESD保护晶体管的复合晶体管结构。触发晶体管包括待保护电路的隔离电压与ESD保护晶体管的击穿电位之间的击穿电位。当激活时，触发晶体管操作以接通被设计为承载与ESD事件相关联的大部分传导电流的ESD保护晶体管。触发晶体管设计有内部增益机制，以确保在ESD保护晶体管操作期间达到修改的快速恢复电压时不会关闭触发晶体管。在保护电路操作时间之后，触发晶体管对ESD保护晶体管的导通电流的影响很小。公开了制造合适的化合物晶体管结构的工艺。

4. 发明授权

US07682918B2 ESD protection for semiconductor products 有权
标题翻译：半导体产品的ESD保护
公开(公告)号：US07682918B2
公开(公告)日：2010-03-23
申请号：US11054189
申请日：2005-02-09
申请人： Jun Cai , Alvin Sugerman , Steven Park
发明人： Jun Cai , Alvin Sugerman , Steven Park
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L27/0266
摘要： A process for forming a vertical DMOS device with an ESD protection transistor that is configured for carrying a breakdown current includes the steps of masking a substrate of a first polarity type and forming spaced apart surface isolation regions. An insulated gate is formed between the spaced apart surface isolation regions. Selected portions of the surface regions between the gate and the surface isolation regions are heterodoped to form p-n junctions having retrograde doping profiles beneath the substrate surface thereby lowering the breakdown voltage beneath the heterodoped portions in order to direct a substantial portion of the breakdown current below the surface of the substrate and into the body of the substrate between the heterodoped regions. Source and drain regions are formed in the substrate surface on opposite sides of the gate.
摘要翻译：用于形成具有用于承载击穿电流的ESD保护晶体管的垂直DMOS器件的工艺包括以下步骤：掩蔽第一极性类型的衬底并形成间隔开的表面隔离区域。在间隔开的表面隔离区域之间形成绝缘栅极。在栅极和表面隔离区域之间的表面区域的选定部分被杂散以形成在衬底表面下方具有逆向掺杂分布的pn结，从而降低异质部分之下的击穿电压，以便将击穿电流的大部分引导到低于衬底的表面并进入到异质区域之间的衬底的主体中。源极和漏极区域形成在栅极的相对侧上的衬底表面中。

5. 发明申请

US20050148124A1 ESD protection for semiconductor products 有权
标题翻译：半导体产品的ESD保护
公开(公告)号：US20050148124A1
公开(公告)日：2005-07-07
申请号：US11054189
申请日：2005-02-09
申请人： Jun Cai , Alvin Sugerman , Steven Park
发明人： Jun Cai , Alvin Sugerman , Steven Park
IPC分类号： H01L20060101 , H01L21/338 , H01L23/62 , H01L27/02 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7833 , H01L27/0266
摘要： A process for forming a vertical DMOS device with an ESD protection transistor that is configured for carrying a breakdown current includes the steps of masking a substrate of a first polarity type and forming spaced apart surface isolation regions. An insulated gate is formed between the spaced apart surface isolation regions. Selected portions of the surface regions between the gate and the surface isolation regions are heterodoped to form p-n junctions having retrograde doping profiles beneath the substrate surface thereby lowering the breakdown voltage beneath the heterodoped portions in order to direct a substantial portion of the breakdown current below the surface of the substrate and into the body of the substrate between the heterodoped regions. Source and drain regions are formed in the substrate surface on opposite sides of the gate.
摘要翻译：用于形成具有用于承载击穿电流的ESD保护晶体管的垂直DMOS器件的工艺包括以下步骤：掩蔽第一极性类型的衬底并形成间隔开的表面隔离区域。在间隔开的表面隔离区域之间形成绝缘栅极。在栅极和表面隔离区域之间的表面区域的选定部分被杂散以形成在衬底表面下方具有逆向掺杂分布的pn结，从而降低异质部分之下的击穿电压，以将击穿电流的大部分引导到低于衬底的表面并进入到异质区域之间的衬底的主体中。源极和漏极区域形成在栅极的相对侧上的衬底表面中。

6. 发明授权

US5246885A Deposition method for high aspect ratio features using photoablation 失效
标题翻译：使用光消融的高纵横比特征的沉积方法
公开(公告)号：US5246885A
公开(公告)日：1993-09-21
申请号：US933951
申请日：1992-08-20
申请人： Bodil E. Braren , Karen H. Brown , Kathleen A. Perry , Rangaswamy Srinivasan , Alvin Sugerman
发明人： Bodil E. Braren , Karen H. Brown , Kathleen A. Perry , Rangaswamy Srinivasan , Alvin Sugerman
IPC分类号： C23C14/28 , H01L21/762 , H01L21/768
CPC分类号： H01L21/76224 , C23C14/28 , H01L21/76879 , Y10S438/94
摘要： A method for providing superior fill of features in semiconductor processing utilizes a laser ablation system. Deposition is obtained by ablating target materials which are driven off perpendicular to the target in the direction of the deposition surface. The method provides complete fill of high aspect ratio features with nominal heating of the substrate. Alloys and graded layers, as well as pure metals, can be deposited in low temperature patterned layers. In addition, the system has been used to achieve superior trench filling for isolation structures.
摘要翻译：在半导体处理中提供优异的特征填充的方法利用了激光烧蚀系统。通过在沉积表面的方向上烧蚀垂直于靶的靶材料来获得沉积。该方法提供了完全填充基材的标称加热的高纵横比特征。合金和分级层以及纯金属可以沉积在低温图案层中。此外，该系统已被用于实现隔离结构的优越的沟槽填充。

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