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1. 发明授权

US07346863B1 Hardware acceleration of high-level language code sequences on programmable devices 有权
标题翻译：可编程器件上的高级语言代码序列的硬件加速
公开(公告)号：US07346863B1
公开(公告)日：2008-03-18
申请号：US11238451
申请日：2005-09-28
申请人： Jeffrey Orion Pritchard , David James Lau , Timothy P. Allen
发明人： Jeffrey Orion Pritchard , David James Lau , Timothy P. Allen
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as memory. A designer efficiently selects one or more code sequences for acceleration. A hardware accelerator is generated with multiple master ports to allow efficient access to memory. Profiling information can be provided to allow efficient selection of code sequences.
摘要翻译：提供了用于实现包括处理器核心，硬件加速器和诸如存储器的次要组件的可编程设备的方法和装置。设计人员有效地选择一个或多个代码序列进行加速。通过多个主端口生成硬件加速器，以便高效地访问内存。可以提供分析信息以允许有效地选择代码序列。

2. 发明授权

US07779286B1 Design tool clock domain crossing management 有权
标题翻译：设计工具时钟域交叉管理
公开(公告)号：US07779286B1
公开(公告)日：2010-08-17
申请号：US11261688
申请日：2005-10-28
申请人： Jeffrey Orion Pritchard , Paul Norbert Scheidt , Timothy P. Allen
发明人： Jeffrey Orion Pritchard , Paul Norbert Scheidt , Timothy P. Allen
IPC分类号： G06F1/04
CPC分类号： G06F17/5045 , G06F17/5054
摘要： Methods and apparatus are provided for allowing efficient clock domain crossing management in programmable chip systems. Components associated with different clock domains can be analyzed. Clock domain crossing components are automatically selected from a library of clock domain crossing components to allow connection between disparate clock domains. Clock domain crossing components can be shared, chained, and intelligently selected for increased efficiency.
摘要翻译：提供了用于允许在可编程芯片系统中有效的时钟域交叉管理的方法和装置。可以分析与不同时钟域相关联的组件。时钟域交叉分量从时钟域交叉组件的库中自动选择，以允许不同时钟域之间的连接。时钟域交叉组件可以共享，链接和智能选择，以提高效率。

3. 发明授权

US08291396B1 Scheduling optimization of aliased pointers for implementation on programmable chips 有权
标题翻译：对可编程芯片实现的别名指针进行调度优化
公开(公告)号：US08291396B1
公开(公告)日：2012-10-16
申请号：US11523261
申请日：2006-09-18
申请人： David James Lau , Jeffrey Orion Pritchard , Philippe Molson
发明人： David James Lau , Jeffrey Orion Pritchard , Philippe Molson
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5054
摘要： Various high-level languages are used to specify hardware designs on programmable chips. The high-level language programs include pointer operations that may have same iteration and future iteration dependencies. Single loop iteration pointer dependencies are considered when memory accesses are assigned to clock cycles. Multiple loop iteration pointer dependencies are considered when determining how often new data can be entered into the generated hardware pipeline without causing memory corruption. A buffer can be used to forward data from a memory write to a future read.
摘要翻译：各种高级语言用于指定可编程芯片上的硬件设计。高级语言程序包括可能具有相同迭代和未来迭代依赖关系的指针操作。当内存访问被分配给时钟周期时，考虑单循环迭代指针依赖关系。当确定新数据可以输入到生成的硬件管道中而不会导致内存损坏时，会考虑多个循环迭代指针依赖关系。可以使用缓冲区将数据从存储器写入转发到未来读取。

4. 发明授权

US07873953B1 High-level language code sequence optimization for implementing programmable chip designs 有权
标题翻译：实现可编程芯片设计的高级语言代码序列优化
公开(公告)号：US07873953B1
公开(公告)日：2011-01-18
申请号：US11385142
申请日：2006-03-20
申请人： Jeffrey Orion Pritchard , Jarrod Colin James Blackburn , David James Lau , Philippe Molson , James L. Ball , Jesse Kempa
发明人： Jeffrey Orion Pritchard , Jarrod Colin James Blackburn , David James Lau , Philippe Molson , James L. Ball , Jesse Kempa
IPC分类号： G06F9/45 , G06F13/28 , G06F17/50
CPC分类号： G06F8/443 , G06F17/5054
摘要： Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences such as high-level language software critical loops are converted into read/transform/write (RXW) processes with buffer based flow control between the processes. Having separate read and write processes allows an arbitrary number of sequential reads/writes to occur in any order, subject to buffer size, allowing bursting/sequential transactions that are more efficient than random accesses.
摘要翻译：提供了使用高级语言来实现可编程芯片的方法和装置。诸如高级语言软件关键环路之类的代码序列被转换为读/写/写（RXW）进程，并且在进程之间使用基于缓冲的流控制。具有单独的读取和写入过程允许任意数量的顺序读取/写入以任何顺序发生，受到缓冲区大小的影响，允许比随机访问更有效的突发/顺序事务。

5. 发明授权

US08286025B1 Selection of port adapters for clock crossing boundaries 有权
标题翻译：选择时钟跨越边界的端口适配器
公开(公告)号：US08286025B1
公开(公告)日：2012-10-09
申请号：US12834980
申请日：2010-07-13
申请人： Jeffrey Orion Pritchard , Paul Norbert Scheidt , Timothy P. Allen
发明人： Jeffrey Orion Pritchard , Paul Norbert Scheidt , Timothy P. Allen
IPC分类号： G06F1/04
CPC分类号： G06F17/5045 , G06F17/5054
摘要： Methods and apparatus are provided for allowing efficient clock domain crossing management in programmable chip systems. Components associated with different clock domains can be analyzed. Clock domain crossing components are automatically selected from a library of clock domain crossing components to allow connection between disparate clock domains. Clock domain crossing components can be shared, chained, and intelligently selected for increased efficiency.
摘要翻译：提供了用于允许在可编程芯片系统中有效的时钟域交叉管理的方法和装置。可以分析与不同时钟域相关联的组件。时钟域交叉分量从时钟域交叉组件的库中自动选择，以允许不同时钟域之间的连接。时钟域交叉组件可以共享，链接和智能选择，以提高效率。

6. 发明授权

US08219785B1 Adapter allowing unaligned access to memory 有权
标题翻译：适配器允许未对齐的内存访问
公开(公告)号：US08219785B1
公开(公告)日：2012-07-10
申请号：US11527201
申请日：2006-09-25
申请人： Timothy P. Allen , Jeffrey Orion Pritchard , Richard Noble Hill
发明人： Timothy P. Allen , Jeffrey Orion Pritchard , Richard Noble Hill
IPC分类号： G06F9/30
CPC分类号： G11C7/22 , G06F12/04
摘要： Methods and apparatus are provided for allowing a master component such as a processor on a programmable chip to access memory using unaligned addresses. An adapter connected to a master component determines if a master component memory access request is aligned. If the access request is aligned, the request is forwarded to memory and a response is provided to the master component. If the access request is unaligned, the adapter sends multiple access requests to memory and processes the responses in order to provide a correct response to the master component.
摘要翻译：提供了用于允许诸如可编程芯片上的处理器的主组件使用未对齐地址访问存储器的方法和装置。连接到主组件的适配器确定主组件存储器访问请求是否对齐。如果访问请求被对齐，则请求被转发到存储器并且向主组件提供响应。如果访问请求未对齐，则适配器向存储器发送多个访问请求并处理响应，以便向主组件提供正确的响应。

7. 发明授权

US08578356B1 High-level language code sequence optimization for implementing programmable chip designs 有权
标题翻译：实现可编程芯片设计的高级语言代码序列优化
公开(公告)号：US08578356B1
公开(公告)日：2013-11-05
申请号：US12966882
申请日：2010-12-13
申请人： Jeffrey Orion Pritchard , Jarrod Colin James Blackburn , David James Lau , Philippe Molson , James L. Ball , Jesse Kempa
发明人： Jeffrey Orion Pritchard , Jarrod Colin James Blackburn , David James Lau , Philippe Molson , James L. Ball , Jesse Kempa
IPC分类号： G06F9/45 , G06F12/00
CPC分类号： G06F8/443 , G06F17/5054
摘要： Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences such as high-level language software critical loops are converted into read/transform/write (RXW) processes with buffer based flow control between the processes. Having separate read and write processes allows an arbitrary number of sequential reads/writes to occur in any order, subject to buffer size, allowing bursting/sequential transactions that are more efficient than random accesses.
摘要翻译：提供了使用高级语言来实现可编程芯片的方法和装置。诸如高级语言软件关键环路之类的代码序列被转换为读/写/写（RXW）进程，并且在进程之间使用基于缓冲的流控制。具有单独的读取和写入过程允许任意数量的顺序读取/写入以任何顺序发生，受到缓冲区大小的影响，允许比随机访问更有效的突发/顺序事务。

8. 发明授权

US07769934B1 Master and slave side arbitrators associated with programmable chip system components 有权
标题翻译：与可编程芯片系统组件相关的主，从侧仲裁器
公开(公告)号：US07769934B1
公开(公告)日：2010-08-03
申请号：US11759828
申请日：2007-06-07
申请人： Jeffrey Orion Pritchard , Timothy P. Allen
发明人： Jeffrey Orion Pritchard , Timothy P. Allen
IPC分类号： G06F13/00
CPC分类号： G06F13/364 , G06F13/374
摘要： Methods and apparatus are provided for providing a first master component with access to a first slave component while a second master component is accessing a second slave component in a system. The system may include a processor core and peripherals implemented on an integrated circuit. A slave side arbitrator corresponding to a single slave component and coupled to multiple master components can be used to provide a master component access to a slave component.
摘要翻译：提供的方法和装置用于在第二主组件正在访问系统中的第二从组件时提供对第一从组件的访问的第一主组件。该系统可以包括在集成电路上实现的处理器核心和外围设备。可以使用对应于单个从属组件并且耦合到多个主组件的从属侧仲裁器来提供主组件对从组件的访问。

9. 发明授权

US08132132B2 Methods and apparatus for implementing parameterizable processors and peripherals 有权
公开(公告)号：US08132132B2
公开(公告)日：2012-03-06
申请号：US11372550
申请日：2006-03-10
申请人： Tim Allen , Michael Fairman , Jeffrey Orion Pritchard , Bryan Hoyer
发明人： Tim Allen , Michael Fairman , Jeffrey Orion Pritchard , Bryan Hoyer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.

10. 发明授权

US08706931B1 Tool selection and implementation of port adapters 有权
标题翻译：端口适配器的工具选择和实现
公开(公告)号：US08706931B1
公开(公告)日：2014-04-22
申请号：US12816316
申请日：2010-06-15
申请人： Jeffrey Orion Pritchard
发明人： Jeffrey Orion Pritchard
IPC分类号： G06F13/12 , G06F13/38
CPC分类号： G06F13/4022
摘要： Methods and apparatus are provided for allowing interconnection between ports associated with primary and secondary components in an embedded system. Ports may only support a particular bus type or set of attributes and a variety of ports may be incompatible. Bus types include Peripheral Components Interface (PCI) and Advanced Microcontroller Bus Architecture (AMBA) while attributes include bursting, non-bursting, word-wide, byte-wide, etc. Port adapters components are automatically selected from a library of port adapter components to allow connection of incompatible ports. Port adapters can be shared, chained, and intelligently selected for increased efficiency.
摘要翻译：提供了用于允许与嵌入式系统中的主要和次要组件相关联的端口之间的互连的方法和装置。端口可能只支持特定的总线类型或一组属性，并且各种端口可能不兼容。总线类型包括外围组件接口（PCI）和高级微控制器总线体系结构（AMBA），而属性包括突发，非突发，字宽，字节范围等。端口适配器组件将从端口适配器组件库中自动选择允许连接不兼容的端口。端口适配器可以共享，链接和智能选择，以提高效率。

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