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    • 9. 发明授权
    • Memory array leakage reduction circuit and method
    • 存储阵列泄漏减少电路及方法
    • US07345947B2
    • 2008-03-18
    • US11516209
    • 2006-09-05
    • Jeffrey L. MillerMahadevamurty NemaniJames W. Conary
    • Jeffrey L. MillerMahadevamurty NemaniJames W. Conary
    • G11C8/00
    • G11C8/08G11C11/413
    • Embodiments of the invention provide techniques for reducing standby power consumption due to leakage currents in memory circuits. In some embodiments, systems are provided with one or more processors having) bit cells coupled to a word-line node and to a virtual ground node. The word-line node is to be at an active word-line voltage when the row is active and an inactive word-line voltage when the row is inactive. The virtual ground node is to be at an operational ground voltage when the memory array is enabled and at an elevated voltage when the memory array is in a standby mode. There is also a word-line driver circuit coupled to the bit cells through the word-line and virtual ground nodes. The current leakage in the bit cells and word-line driver circuit is reduced during the standby mode when the virtual ground node is at the elevated voltage.
    • 本发明的实施例提供了用于减少由于存储器电路中的漏电流引起的待机功耗的技术。 在一些实施例中,系统具有一个或多个处理器,其具有耦合到字线节点和虚拟接地节点的位单元。 当行处于活动状态时,字线节点将处于活动字线电压,而当行处于非活动状态时,字线节点处于活动字线电压。 当存储器阵列被使能并且当存储器阵列处于待机模式时处于升高的电压时,虚拟接地节点将处于操作接地电压。 还有通过字线和虚拟接地节点耦合到位单元的字线驱动电路。 当虚拟接地节点处于升高的电压时,在待机模式期间,位单元和字线驱动电路中的电流泄漏减小。