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1. 发明授权

US08069023B1 Hardware support for instruction set emulation 有权
标题翻译：硬件支持指令集仿真
公开(公告)号：US08069023B1
公开(公告)日：2011-11-29
申请号：US12202742
申请日：2008-09-02
申请人： Jean-Marc Frailong , Jeffrey G. Libby , Jianhui Huang , Sharada Yeluri , Rajesh Nair , John Keen
发明人： Jean-Marc Frailong , Jeffrey G. Libby , Jianhui Huang , Sharada Yeluri , Rajesh Nair , John Keen
IPC分类号： G06F17/50
CPC分类号： G06F9/3004 , G06F9/30145 , G06F9/30174 , G06F9/32 , H04L45/745
摘要： A method for emulating a nexthop instruction in microcode with the assistance of dedicated hardware to extract read and write addressing from the nexthop instruction instead of performing this operation in microcode. A method for emulating a nexthop instruction in microcode with the assistance of dedicated hardware to compare a nexthop read address to a special value and to indicate whether the nexthop read address matches the special value, instead of performing this operation in microcode. A method for determining a network address by performing a single extraction of bit fields of a tree instruction to allow multiple tree search processes to be performed.
摘要翻译：一种在专用硬件协助下仿真微代码中的下一跳指令的方法，用于从下一跳指令中提取读取和写入寻址，而不是在微码中执行该操作。一种在专用硬件的协助下仿真微代码中的下一跳指令的方法，用于将下一跳读取地址与特殊值进行比较，并指示下一跳读取地址是否匹配特殊值，而不是以微码执行该操作。一种通过执行树指令的位字段的单次提取来确定网络地址以允许执行多个树搜索处理的方法。

2. 发明授权

US09026424B1 Emulation of multiple instruction sets 有权
标题翻译：仿真多个指令集
公开(公告)号：US09026424B1
公开(公告)日：2015-05-05
申请号：US12258487
申请日：2008-10-27
申请人： Jeffrey G. Libby , Jean-Marc Frailong , Sharada Yeluri , Jianhui Huang , John Keen , Rajesh Nair
发明人： Jeffrey G. Libby , Jean-Marc Frailong , Sharada Yeluri , Jianhui Huang , John Keen , Rajesh Nair
IPC分类号： G06F9/455 , G06F12/00 , G06F17/50
CPC分类号： G06F9/455 , G06F9/45504 , G06F12/00 , G06F17/50
摘要： A device may emulate target instructions by executing a first set of microinstructions, and may store a base address of a table that includes a microinstruction provided in a second set of microinstructions for emulating the target instructions. The device may also locate the microinstruction based on the stored base address, and emulate one of the target instructions by executing the microinstruction.
摘要翻译：设备可以通过执行第一组微指令来模拟目标指令，并且可以存储包括在第二组微指令中提供的用于模拟目标指令的微指令的表的基地址。设备还可以基于存储的基地址定位微指令，并且通过执行微指令来模拟目标指令之一。

3. 发明授权

US08520675B1 System and method for efficient packet replication 有权
标题翻译：高效的数据包复制的系统和方法
公开(公告)号：US08520675B1
公开(公告)日：2013-08-27
申请号：US12343276
申请日：2008-12-23
申请人： Jean-Marc Frailong , Jeffrey G. Libby , Anurag P. Gupta , John Keen , Rajesh Nair , Avanindra Godbole , Sharada Yeluri
发明人： Jean-Marc Frailong , Jeffrey G. Libby , Anurag P. Gupta , John Keen , Rajesh Nair , Avanindra Godbole , Sharada Yeluri
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L45/56 , H04L45/16 , H04L49/10 , H04L49/90
摘要： Methods and systems consistent with the present invention provide efficient packet replication in a router in order to multicast a stream of data. Packets are replicated and processed in a multithreaded environment. Embodiments consistent with the present invention implement a two-stage process for packet replication. The first stage thread will recirculate the packet to multiple second-stage threads. These second-stage threads will then create one or more outgoing copies of the packet. In this way, the copies are handled by multiple threads running in parallel.
摘要翻译：与本发明一致的方法和系统在路由器中提供有效的分组复制以便多播数据流。数据包在多线程环境中进行复制和处理。与本发明一致的实施例实现了用于分组复制的两阶段过程。第一级线程将数据包循环到多个第二级线程。这些第二级线程将会创建一个或多个数据包的输出副本。以这种方式，副本由并行运行的多个线程处理。

4. 发明授权

US08880856B1 Efficient arithmetic logic units 有权
标题翻译：高效的算术逻辑单元
公开(公告)号：US08880856B1
公开(公告)日：2014-11-04
申请号：US12486114
申请日：2009-06-17
申请人： Jean-Marc Frailong , Pradeep Sindhu , Jeffrey G. Libby , Jian Hui Huang , Rajesh Nair , John Keen
发明人： Jean-Marc Frailong , Pradeep Sindhu , Jeffrey G. Libby , Jian Hui Huang , Rajesh Nair , John Keen
IPC分类号： G06F15/00
CPC分类号： G06F9/28 , G06F7/57 , G06F9/30 , G06F9/3001 , G06F9/30018 , G06F9/30072 , G06F9/30145 , G06F9/3859 , G06F9/3893 , G06F15/00
摘要： A processor may include a conditional arithmetic logic unit and a main arithmetic logic unit. The conditional arithmetic logic unit may perform a first arithmetic logic operation to generate a first result, and output the result. The main arithmetic logic unit may select input buses among a plurality of data buses that carry the first result from the conditional arithmetic logic unit, perform a second arithmetic logic operation on data provided by the selected input buses to generate a second result, and write the second result in a storage component.
摘要翻译：处理器可以包括条件算术逻辑单元和主算术逻辑单元。条件算术逻辑单元可以执行第一算术逻辑运算以产生第一结果，并输出结果。主算术逻辑单元可以选择携带来自条件算术逻辑单元的第一结果的多个数据总线中的输入总线，对由所选择的输入总线提供的数据执行第二运算逻辑运算以产生第二结果，并写入第二个结果是存储组件。

5. 发明申请

US20070043871A1 Debug non-terminal symbol for parser error handling 审中-公开
标题翻译：调试解析器错误处理的非终端符号
公开(公告)号：US20070043871A1
公开(公告)日：2007-02-22
申请号：US11185223
申请日：2005-07-19
申请人： Jonathan Sweedler , Rajesh Nair , Komal Rathi , Kevin Rowett
发明人： Jonathan Sweedler , Rajesh Nair , Komal Rathi , Kevin Rowett
IPC分类号： G06F15/16
CPC分类号： H04L69/22
摘要： A device has an input port to allow the device to receive data. The device also has a parser to parse the data in response to symbols in a parser stack, determine when a symbol is a debug non-terminal symbol, and notify the device via an interrupt. The interrupt causes the device to gather information about the state of the parser at the time of encountering the non-terminal symbol.
摘要翻译：设备具有允许设备接收数据的输入端口。该设备还具有解析器，以响应解析器堆栈中的符号来解析数据，确定符号是否为调试非终端符号，并通过中断通知设备。中断使设备在遇到非终端符号时收集有关解析器状态的信息。

6. 发明申请

US20070019661A1 Packet output buffer for semantic processor 审中-公开
标题翻译：语义处理器的数据包输出缓冲区
公开(公告)号：US20070019661A1
公开(公告)日：2007-01-25
申请号：US11186144
申请日：2005-07-20
申请人： Kevin Rowett , Rajesh Nair , Caveh Jalali , Joel Lach
发明人： Kevin Rowett , Rajesh Nair , Caveh Jalali , Joel Lach
IPC分类号： H04L12/56
CPC分类号： G06F8/427 , H04L49/90 , H04L69/12 , H04L69/22
摘要： An embodiment of the invention is a processor comprising a direct execution parser configured to control the processing of digital data by semantically parsing data; a plurality of semantic processing units configured to perform data operations when prompted by the direct execution parser; and a plurality of output buffers for buffering data received from the plurality of semantic processing units. Another embodiment of the invention is an interface circuit comprising a packer circuit for receiving data from a semantic processing unit and a plurality of buffers for receiving the data. The interface circuit unloads the data received to an interface.
摘要翻译：本发明的实施例是一种处理器，包括：配置成通过语义地解析数据来控制数字数据的处理的直接执行解析器; 多个语义处理单元，被配置为当由直接执行解析器提示时执行数据操作; 以及多个输出缓冲器，用于缓冲从多个语义处理单元接收的数据。本发明的另一实施例是一种接口电路，包括用于从语义处理单元接收数据的封隔器电路和用于接收数据的多个缓冲器。接口电路将接收的数据卸载到接口。

7. 发明申请

US20050218431A1 High voltage lateral FET structure with improved on resistance performance 有权
标题翻译：高电压横向FET结构，具有改进的导通电阻性能
公开(公告)号：US20050218431A1
公开(公告)日：2005-10-06
申请号：US10797537
申请日：2004-03-11
申请人： Rajesh Nair , Shanghui Tu , Zia Hossain , Mohammed Quddus
发明人： Rajesh Nair , Shanghui Tu , Zia Hossain , Mohammed Quddus
IPC分类号： H01L29/06 , H01L29/423 , H01L29/78 , H01L29/80
CPC分类号： H01L29/0634 , H01L29/42368 , H01L29/7809 , H01L29/7816 , H01L29/7825
摘要： In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The body of semiconductor material includes alternating layers of opposite conductivity type that extend between a trench drain region and a trench gate structure. The trench gate structure controls at least one sub-surface channel region. The body of semiconductor material provides sub-surface drift regions to reduce on resistance without increasing device area.
摘要翻译：在一个实施例中，在半导体材料体中形成横向FET单元。半导体材料的主体包括在沟槽漏极区域和沟槽栅极结构之间延伸的相反导电类型的交替层。沟槽栅极结构控制至少一个子表面沟道区域。半导体材料的主体提供了亚表面漂移区域以减少导通电阻而不增加器件面积。

8. 发明申请

US20050153512A1 Method of forming an EPROM cell and structure therefor 有权
标题翻译：形成EPROM单元的方法及其结构
公开(公告)号：US20050153512A1
公开(公告)日：2005-07-14
申请号：US10752772
申请日：2004-01-08
申请人： Gennadiy Nemtsev , Yingping Zheng , Rajesh Nair
发明人： Gennadiy Nemtsev , Yingping Zheng , Rajesh Nair
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , G11C2216/10 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/66825
摘要： An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate.
摘要翻译： EPROM单元包括控制栅极和控制晶体管。控制晶体管的一部分形成为控制栅极的一部分。

9. 发明申请

US20120290317A1 TOOL FOR CLINICAL DATA MINING AND ANALYSIS 审中-公开
标题翻译：临床数据挖掘和分析工具
公开(公告)号：US20120290317A1
公开(公告)日：2012-11-15
申请号：US13522711
申请日：2011-01-21
申请人： Rajesh Nair , Sanjay Parikh
发明人： Rajesh Nair , Sanjay Parikh
IPC分类号： G06Q50/22
CPC分类号： G06Q50/22 , G06Q10/10
摘要： In one aspect, the invention provides a clinical trial information management tool. The tool comprises an interface with a multiple tagged clinical trial database; a user interface for receiving user inputs, a search engine to query the multiple tagged clinical trial database in one or more levels based on user inputs; a display platform to display results from the query in one or more views; an analytics engine to provide at least one of parameter based analysis and graphical analysis; and a personalization platform to store the query and the results. The tool provides the advantage through the rapid, facile and user-friendly manner in which clinical trial information from a wide variety of sources may be searched, analyzed and reported by a user, which allows for easy strategizing regarding clinical trial related matters, among other unique advantages.
摘要翻译：一方面，本发明提供临床试验信息管理工具。该工具包括具有多标签临床试验数据库的界面; 用于接收用户输入的用户界面;搜索引擎，用于基于用户输入以一个或多个级别查询所述多标签临床试验数据库; 显示平台，用于在一个或多个视图中显示来自查询的结果; 分析引擎，提供基于参数的分析和图形分析中的至少一个; 以及个性化平台来存储查询和结果。该工具通过快速，轻松和用户友好的方式提供优势，其中来自各种来源的临床试验信息可由用户进行搜索，分析和报告，这允许在临床试验相关事项方面进行简单的策略化独特的优势。

10. 发明申请

US20060010193A1 Parser table/production rule table configuration using CAM and SRAM 失效
标题翻译：使用CAM和SRAM的解析器表/生产规则表配置
公开(公告)号：US20060010193A1
公开(公告)日：2006-01-12
申请号：US11181527
申请日：2005-07-14
申请人： Somsubhra Sikdar , Kevin Rowett , Rajesh Nair , Komal Rathi
发明人： Somsubhra Sikdar , Kevin Rowett , Rajesh Nair , Komal Rathi
IPC分类号： G06F15/16
CPC分类号： G06F9/45508 , G06F8/427 , H04L41/0893 , H04L45/7453 , H04L49/90 , H04L69/12 , H04L69/22
摘要： A system and method for parsing a data stream comprises a production rule table populated with production rules, a parser table populated with production rule codes that correspond to production rules within the production rule table, and a direct execution parser to identify production rule codes in the parser table and to retrieve production rules from the production rule table according to the identified production rule codes, the direct execution parser is operable to parse a data stream according to the retrieved production rules.
摘要翻译：用于解析数据流的系统和方法包括填充有生产规则的生产规则表，填充有与生产规则表内的生产规则对应的生产规则代码的解析器表以及用于识别生产规则代码中的生产规则代码的直接执行解析器解析器表，并且根据所识别的生产规则代码从生产规则表中检索生产规则，直接执行解析器可操作以根据所检索的生产规则解析数据流。

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