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    • 1. 发明申请
    • Semiconductor switch
    • 半导体开关
    • US20080237630A1
    • 2008-10-02
    • US12079841
    • 2008-03-27
    • Jeffrey G. BarrowJavier A. SalcedoA. Paul Brokaw
    • Jeffrey G. BarrowJavier A. SalcedoA. Paul Brokaw
    • H01L29/745
    • H01L29/745H01L29/7408H01L29/7455
    • A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor.
    • 半导体开关包括被布置为提供类SCR功能的PNPN结构,以及优选地集成在公共基板上的MOS栅极结构。 该开关包括用于MOS栅极的欧姆接触,以及用于PNPN结构的阴极和栅极区域; 阳极接触是固有的。 固定电压通常被施加到外部节点。 MOS栅极结构允许在导通时在外部节点和本征阳极之间传导电流,并且当适当的电压施加到栅极触点时,PNPN结构将电流从阳极传导到阴极。 再生反馈一旦开始进行就保持开关状态。 MOS门禁止外部节点和阳极之间的电流流动,从而在关闭时关闭开关。 当导通时,MOS栅极的沟道电阻用作镇流电阻。
    • 2. 发明授权
    • Semiconductor switch
    • 半导体开关
    • US08519432B2
    • 2013-08-27
    • US12079841
    • 2008-03-27
    • Jeffrey G. BarrowJavier A. SalcedoA. Paul Brokaw
    • Jeffrey G. BarrowJavier A. SalcedoA. Paul Brokaw
    • H01L29/66
    • H01L29/745H01L29/7408H01L29/7455
    • A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor.
    • 半导体开关包括被布置为提供类SCR功能的PNPN结构,以及优选地集成在公共基板上的MOS栅极结构。 该开关包括用于MOS栅极的欧姆接触,以及用于PNPN结构的阴极和栅极区域; 阳极接触是固有的。 固定电压通常被施加到外部节点。 MOS栅极结构允许在导通时在外部节点和本征阳极之间传导电流,并且当适当的电压施加到栅极触点时,PNPN结构将电流从阳极传导到阴极。 再生反馈一旦开始进行,就保持开关状态。 MOS门禁止外部节点和阳极之间的电流流动,从而在关闭时关闭开关。 当导通时,MOS栅极的沟道电阻用作镇流电阻。
    • 3. 发明授权
    • Error amplifier structures
    • 误差放大器结构
    • US07847634B2
    • 2010-12-07
    • US12321708
    • 2009-01-22
    • Jeffrey G. BarrowA. Paul Brokaw
    • Jeffrey G. BarrowA. Paul Brokaw
    • H03F3/45
    • H03F3/45475H03F3/347
    • Error amplifier structures are provided to generate an error signal in response to the difference between an input signal (e.g., a feedback current) and a reference signal (e.g., a bias current). Amplifier embodiments generally include a reference generator and a differencing amplifier. In at least one embodiment, the error generator is arranged to generate first and second bias voltages that correspond to the bias current. In at least one embodiment, the differencing amplifier is configured to provide a reference current to an output node in response to the first bias voltage, provide a feedback current to the output node in response to the second bias voltage, and generate an error current in response to a voltage at the output node. The error amplifier structures are suited for use in various systems such as negative switching regulators.
    • 提供误差放大器结构以响应于输入信号(例如,反馈电流)和参考信号(例如,偏置电流)之间的差异来产生误差信号。 放大器实施例通常包括参考发生器和差分放大器。 在至少一个实施例中,误差发生器被布置成产生对应于偏置电流的第一和第二偏置电压。 在至少一个实施例中,差分放大器被配置为响应于第一偏置电压向输出节点提供参考电流,响应于第二偏置电压向输出节点提供反馈电流,并且产生误差电流 响应于输出节点处的电压。 误差放大器结构适用于各种系统,如负开关稳压器。
    • 4. 发明申请
    • APPARATUSES AND METHODS FOR REDUCING POWER IN DRIVING DISPLAY PANELS
    • 驱动显示面板降低功率的装置和方法
    • US20120223647A1
    • 2012-09-06
    • US13040077
    • 2011-03-03
    • A. Paul BrokawJune HerJeffrey G. Barrow
    • A. Paul BrokawJune HerJeffrey G. Barrow
    • H05B37/00
    • G09G3/3648G09G3/3614G09G3/3688G09G3/3696G09G2330/024G09G2330/028
    • Energy sharing circuits and related methods are disclosed herein. A high voltage can be selectively coupled to a first source line and a low voltage can be selectively coupled to a second source line during a first time period. During a subsequent time period, a first coupling switch is activated to inductively couple the first source line to the second source line and diode block the second source line from the first source line. During a subsequent time period, the low voltage is selectively coupled to the first source line and the high voltage is selectively coupled to the second source line. During a subsequent time period, a second coupling switch is activated to inductively couple the second source line to the first source line and diode block the first source line from the second source line.
    • 本文公开了能量共享电路和相关方法。 高电压可以选择性地耦合到第一源极线,并且低电压可以在第一时间周期期间选择性地耦合到第二源极线。 在随后的时间段期间,激活第一耦合开关以将第一源极线耦合到第二源极线,并且将第二源极线与第一源极线截取二极管。 在随后的时间段期间,低电压选择性地耦合到第一源极线,并且高电压选择性地耦合到第二源极线。 在随后的时间段期间,激活第二耦合开关以将第二源极线耦合到第一源极线,并且将第二源极线与第二源极线截获。
    • 6. 发明授权
    • Apparatuses and methods for reducing power in driving display panels
    • 驱动显示面板的功率降低的装置和方法
    • US08624818B2
    • 2014-01-07
    • US13040077
    • 2011-03-03
    • A. Paul BrokawJune HerJeffrey G. Barrow
    • A. Paul BrokawJune HerJeffrey G. Barrow
    • G09G3/36
    • G09G3/3648G09G3/3614G09G3/3688G09G3/3696G09G2330/024G09G2330/028
    • Energy sharing circuits and related methods are disclosed herein. A high voltage can be selectively coupled to a first source line and a low voltage can be selectively coupled to a second source line during a first time period. During a subsequent time period, a first coupling switch is activated to inductively couple the first source line to the second source line and diode block the second source line from the first source line. During a subsequent time period, the low voltage is selectively coupled to the first source line and the high voltage is selectively coupled to the second source line. During a subsequent time period, a second coupling switch is activated to inductively couple the second source line to the first source line and diode block the first source line from the second source line.
    • 本文公开了能量共享电路和相关方法。 高电压可以选择性地耦合到第一源极线,并且低电压可以在第一时间周期期间选择性地耦合到第二源极线。 在随后的时间段期间,激活第一耦合开关以将第一源极线耦合到第二源极线,并且将第二源极线与第一源极线截取二极管。 在随后的时间段期间,低电压选择性地耦合到第一源极线,并且高电压选择性地耦合到第二源极线。 在随后的时间段期间,激活第二耦合开关以将第二源极线耦合到第一源极线,并且将第二源极线与第二源极线截获。
    • 8. 发明申请
    • LOW ON-RESISTANCE POWER TRANSISTOR, POWER CONVERTER, AND RELATED METHOD
    • 低电阻功率晶体管,功率转换器及相关方法
    • US20120235241A1
    • 2012-09-20
    • US13048726
    • 2011-03-15
    • Jeffrey G. Barrow
    • Jeffrey G. Barrow
    • H01L27/088G06F17/50
    • H01L27/088H01L27/0207
    • A power transistor and a power converter are disclosed that may improve the on-resistance and corresponding silicon area of a power transistor. The power transistor may comprise a drain, a source, and a channel therebetween divided into a plurality of transistor stripes, the plurality of transistor stripes being grouped in a plurality of different groups. The power transistor may further comprise a first top metal associated with one of the drain and the source, and a second top metal associated with the other of the drain and the source. The second top metal includes at least one portion that is coupled to different groups of transistor stripes. A related method for determining a layout topology of a power transistor is also disclosed.
    • 公开了功率晶体管和功率转换器,其可以改善功率晶体管的导通电阻和对应的硅面积。 功率晶体管可以包括漏极,源极和它们之间的沟道,被分成多个晶体管条,多个晶体管条被分组成多个不同的组。 功率晶体管还可以包括与漏极和源极之一相关联的第一顶部金属和与漏极和源极中的另一个相关联的第二顶部金属。 第二顶部金属包括耦合到不同组的晶体管条纹的至少一​​个部分。 还公开了用于确定功率晶体管的布局拓扑的相关方法。
    • 9. 发明授权
    • Temperature-compensation networks
    • 温度补偿网络
    • US08159448B2
    • 2012-04-17
    • US12317108
    • 2008-12-19
    • Jeffrey G. Barrow
    • Jeffrey G. Barrow
    • G09G3/36
    • G05F3/16
    • Temperature-compensation network embodiments are provided to generate compensation signals which may be useful in improving the performance of a variety of important systems. An embodiment includes a limit current mirror configured to provide a limit current, a current generator to provide a slope current whose magnitude varies with temperature, and an output current mirror positioned to receive the limit current and the slope current and configured to provide a compensation current. In addition, a floating voltage reference is provided for use in various networks which include the temperature-compensation networks. The temperature-compensation networks may be used to improve performance in systems such as a panel driver which provides turn-on and turn-off gate voltages to transistors in liquid crystal displays.
    • 提供温度补偿网络实施例以产生可用于改善各种重要系统的性能的补偿信号。 一个实施例包括配置成提供限制电流的限流电流镜,电流发生器以提供其幅度随温度变化的斜率电流,以及定位成接收限制电流和斜率电流并被配置为提供补偿电流的输出电流镜 。 另外,提供浮动电压基准用于包括温度补偿网络的各种网络中。 温度补偿网络可以用于提高系统中的性能,例如面板驱动器,其提供液晶显示器中的晶体管的导通和截止栅极电压。
    • 10. 发明授权
    • Apparatuses and methods for a level shifter with reduced shoot-through current
    • 具有降低直通电流的电平转换器的装置和方法
    • US08004339B2
    • 2011-08-23
    • US12622266
    • 2009-11-19
    • Jeffrey G. Barrow
    • Jeffrey G. Barrow
    • H03L5/00
    • H03K19/0008H03K19/018521
    • A level-shifting circuit with reduced shoot-through current includes an output circuit comprising high-voltage devices with a pull-up circuit configured for pulling up a voltage on an output signal to a high voltage responsive to a high-side control signal. The output circuit may also include a pull-down circuit configured for pulling down the voltage on the output signal to a low voltage in responsive to a low-side control signal. The level-shifting circuit can also include a high-side inverting buffer operably coupled between an edge-controlled signal and the high-side control signal, and a low-side buffer configured for driving the low-side control signal responsive to an input signal. The level-shifting circuit may also include an edge-control buffer operably coupled between the input signal and the high-side inverting buffer and configured to generate the edge-controlled signal with a slow rise time relative to a fall time.
    • 具有降低的直通电流的电平移动电路包括输出电路,其包括具有上拉电路的高电压装置,该上拉电路被配置为响应于高侧控制信号将输出信号上的电压提升到高电压。 输出电路还可以包括下拉电路,其被配置为响应于低侧控制信号而将输出信号上的电压降低到低电压。 电平移位电路还可以包括可操作地耦合在边缘控制信号和高侧控制信号之间的高侧反相缓冲器,以及响应于输入信号而驱动低侧控制信号的低侧缓冲器 。 电平移位电路还可以包括边缘控制缓冲器,其可操作地耦合在输入信号和高侧反相缓冲器之间,并被配置为相对于下降时间产生具有缓慢上升时间的边沿控制信号。