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1. 发明授权

US5242711A Nucleation control of diamond films by microlithographic patterning 失效
标题翻译：通过微光刻图案对金刚石膜的成核控制
公开(公告)号：US5242711A
公开(公告)日：1993-09-07
申请号：US746458
申请日：1991-08-16
申请人： Jeffrey D. DeNatale , John F. Flintoff , Alan B. Harker , Patrick J. Hood , Gerald D. Robinson
发明人： Jeffrey D. DeNatale , John F. Flintoff , Alan B. Harker , Patrick J. Hood , Gerald D. Robinson
IPC分类号： B81B3/00 , B81C99/00 , C23C16/02 , C23C16/27 , G02B1/11 , G03F7/00
CPC分类号： G02B1/118 , B81C1/00111 , B81C1/00198 , B81C1/0038 , C23C16/0227 , C23C16/0272 , C23C16/274 , C23C16/277 , G03F7/00 , B81B2201/035 , B81B2201/047 , B81C2201/0191 , B81C2201/056 , Y10T428/30
摘要： A high temperature resist process is combined with microlithographic patterning for the production of materials, such as diamond films, that require a high temperature deposition environment. A conventional polymeric resist process may be used to deposit a pattern of high temperature resist material. With the high temperature resist in place and the polymeric resist removed, a high temperature deposition process may proceed without degradation of the resist pattern. After a desired film of material has been deposited, the high temperature resist is removed to leave the film in the pattern defined by the resist. For diamond films, a high temperature silicon nitride resist can be used for microlithographic patterning of a silicon substrate to provide a uniform distribution of diamond nucleation sites and to improve diamond film adhesion to the substrate. A fine-grained nucleation geometry, established at the nucleation sites, is maintained as the diamond film is deposited over the entire substrate after the silicon nitride resist is removed. The process can be extended to form microstructures of fine-grained polycrystalline diamond, such as rotatable microgears and surface relief patterns, that have the desirable characteristics of hardness, wear resistance, thermal conductivity, chemical inertness, anti-reflectance, and a low coefficient of friction.
摘要翻译：将高温抗蚀剂工艺与用于生产需要高温沉积环境的材料（例如金刚石膜）的微光刻图案组合。传统的聚合物抗蚀剂工艺可用于沉积耐高温材料的图案。通过将高温抗蚀剂置于适当位置并除去聚合物抗蚀剂，可以进行高温沉积工艺而不降解抗蚀剂图案。在已经沉积所需的材料膜之后，去除高温抗蚀剂以使膜以由抗蚀剂限定的图案离开。对于金刚石膜，可以使用高温氮化硅抗蚀剂用于硅衬底的微光刻图案以提供金刚石成核位点的均匀分布并且改善金刚石膜对衬底的粘附。在去除氮化硅抗蚀剂之后，在整个衬底上沉积金刚石膜，保持在成核位置建立的细晶粒成核几何形状。该方法可以扩展以形成具有期望的硬度，耐磨性，导热性，化学惰性，抗反射性和低系数的细晶粒多晶金刚石的微观结构，例如可旋转的微观尺寸和表面浮雕图案摩擦。

2. 发明授权

US5663075A Method of fabricating backside illuminated FET optical receiver with gallium arsenide species 失效
标题翻译：制造具有砷化镓种类的背面照明FET光接收器的方法
公开(公告)号：US5663075A
公开(公告)日：1997-09-02
申请号：US274931
申请日：1994-07-14
申请人： Gerald D. Robinson
发明人： Gerald D. Robinson
IPC分类号： H01L29/812 , H01L31/0352 , H01L31/112 , H01L31/18 , H01L21/20 , H01L21/203 , H01L21/265
CPC分类号： H01L31/1844 , H01L29/8126 , H01L31/0352 , H01L31/1123 , H01L31/1126 , Y02E10/544 , Y10S438/977 , Y10S438/98
摘要： A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration and then inverted onto a new permanent substrate member and an original surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Electrical characteristics including curve tracer electrical data originating in both dark and illuminated devices and devices of varying size and both depletion mode and enhancement mode operation are also disclosed. Fabrication of the device from gallium arsenide semiconductor material and utilization for infrared energy transducing in a number of differing electronic applications are also disclosed.
摘要翻译：公开了一种具有大面积背面光能接收表面的光电FET器件。光源FET器件以源栅极和漏极向上配置制造，然后被倒置到新的永久性衬底构件上，并且去除原始替代衬底构件以暴露有源区域背面光能接收表面。还公开了包括起源于暗和照明装置的曲线跟踪器电数据和不同大小以及耗尽模式和增强模式操作两者的电特性。还公开了从砷化镓半导体材料制造器件和在许多不同的电子应用中利用红外能量转换的方法。

3. 发明授权

US5804847A Backside illuminated FET optical receiver with gallium arsenide species 失效
标题翻译：背面照明FET光接收器与砷化镓种类
公开(公告)号：US5804847A
公开(公告)日：1998-09-08
申请号：US577995
申请日：1995-12-22
申请人： Gerald D. Robinson
发明人： Gerald D. Robinson
IPC分类号： H01L29/812 , H01L31/0352 , H01L31/112 , H01L31/18 , H01L29/80 , H01L31/0288
CPC分类号： H01L31/1844 , H01L29/8126 , H01L31/0352 , H01L31/1123 , H01L31/1126 , Y02E10/544 , Y10S438/977 , Y10S438/98
摘要： A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration and then inverted onto a new permanent substrate member and an original surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Electrical characteristics including curve tracer electrical data originating in both dark and illuminated devices and devices of varying size and both depletion mode and enhancement mode operation are also disclosed. Fabrication of the device from gallium arsenide semiconductor material and utilization for infrared energy transducing in a number of differing electronic applications are also disclosed.
摘要翻译：公开了一种具有大面积背面光能接收表面的光电FET器件。光源FET器件以源栅极和漏极向上配置制造，然后反转到新的永久性衬底构件上，并且去除原始替代衬底构件以暴露有源区域背面光能接收表面。还公开了包括起源于暗和照明装置的曲线跟踪器电数据和不同大小以及耗尽模式和增强模式操作两者的电特性。还公开了从砷化镓半导体材料制造器件和在许多不同的电子应用中利用红外能量转换的方法。

4. 发明授权

US5811322A Method of making a broadband backside illuminated MESFET with collecting microlens 失效
标题翻译：制造具有收集微透镜的宽带背面照明MESFET的方法
公开(公告)号：US5811322A
公开(公告)日：1998-09-22
申请号：US679880
申请日：1996-07-15
申请人： Gerald D. Robinson
发明人： Gerald D. Robinson
IPC分类号： H01L31/0232 , H01L31/112 , H01L21/84
CPC分类号： H01L31/0232 , H01L31/1123
摘要： A composite-layer semiconductor device includes a gate above a host substrate, an n++ contact layer above the gate, and source and drain ohmic contacts applied to the n++ contact layer. The source and drain ohmic contacts define a central gate location which is recessed through the n++ contact layer toward the gate. The source and drain ohmic contacts create a barrier to chemical etching so that a current path below the central gate location can be incrementally recessed in repeated steps to precisely tailor the operating mode of the device for depletion or enhancement applications. The composite-layer semiconductor device is fabricated by depositing a gate on an n++ contact layer above a semi-insulating substrate. The semi-insulating substrate and gate are flipped onto an epoxy layer on the host substrate so that the gate is secured to the epoxy layer and the semi-insulating substrate presents an exposed backside. A portion of the exposed backside is removed. The source and drain ohmic contacts are applied to the exposed backside. The exposed backside is recessed at the central gate location to define the current path which connects the source and drain ohmic contacts.
摘要翻译：复合层半导体器件包括在主体衬底上方的栅极，栅极上方的n ++接触层以及施加到n ++接触层的源极和漏极欧姆接触。源极和漏极欧姆触点限定了通过n ++接触层向栅极凹陷的中心栅极位置。源极和漏极欧姆触点产生化学蚀刻的障碍，使得在中心栅极位置下方的电流路径可以以重复的步骤递增地凹入，以精确地定制用于耗尽或增强应用的器件的操作模式。通过在半绝缘基板上方的n ++接触层上沉积栅极来制造复合层半导体器件。半绝缘基板和栅极被翻转到主基板上的环氧树脂层上，使得栅极固定到环氧树脂层，半绝缘基板呈现暴露的背面。暴露背面的一部分被去除。源极和漏极欧姆接触应用于暴露的背面。暴露的背面凹陷在中央门位置以限定连接源极和漏极欧姆接触的电流路径。

5. 发明授权

US5147740A Structure and process for fabricating conductive patterns having sub-half micron dimensions 失效
标题翻译：用于制造具有半微米尺寸的导电图案的结构和工艺
公开(公告)号：US5147740A
公开(公告)日：1992-09-15
申请号：US564996
申请日：1990-08-09
申请人： Gerald D. Robinson
发明人： Gerald D. Robinson
IPC分类号： G03F7/09 , H01L21/027 , H01L21/285 , H01L21/335 , H01L21/338
CPC分类号： H01L29/66863 , G03F7/094 , H01L21/0272 , H01L21/28587 , H01L29/66462
摘要： A mask and lithographic process is disclosed for the formation of conductive patterns on substrates, particularly in connection with the formation of high electron mobility transistors (HEMT) and metal-semiconductor field effect transistors (MESFET). The technique allows the formation of sub-half micron conductive patterns on semiconductor substrates using optical lithography and a multilayer portable conformable mask. The method includes the application of optical contact lithography to a conventional photoresist followed by a deep UV flood exposure of an underlying multilayer PMGI portion. Metal is deposited on a semiconductor substrate through the mask formed by the photoresist and PMGI layers to produce sub-half micron conductive patterns.
摘要翻译：公开了用于在衬底上形成导电图案的掩模和光刻工艺，特别是与高电子迁移率晶体管（HEMT）和金属 - 半导体场效应晶体管（MESFET）的形成有关。该技术允许使用光学平版印刷术和多层便携式适形掩模在半导体衬底上形成半微米的导电图案。该方法包括将光学接触光刻应用于常规光致抗蚀剂，然后对下面的多层PMGI部分进行深紫外线曝光。金属通过由光致抗蚀剂和PMGI层形成的掩模沉积在半导体衬底上，以产生半微米的导电图案。

6. 发明授权

US6078070A Broadband backside illuminated MESFET with collecting microlens 失效
标题翻译：带收集微透镜的宽带背面照明MESFET
公开(公告)号：US6078070A
公开(公告)日：2000-06-20
申请号：US4141
申请日：1998-01-07
申请人： Gerald D. Robinson
发明人： Gerald D. Robinson
IPC分类号： H01L31/0232 , H01L31/112 , H01L29/80 , H01L31/062
CPC分类号： H01L31/0232 , H01L31/1123
摘要： A composite-layer semiconductor device includes a gate above a host substrate, an n++ contact layer above the gate, and source and drain ohmic contacts applied to the n++ contact layer. The source and drain ohmic contacts define a central gate location which is recessed through the n++ contact layer toward the gate. The source and drain ohmic contacts create a barrier to chemical etching so that a current path below the central gate location can be incrementally recessed in repeated steps to precisely tailor the operating mode of the device for depletion or enhancement applications. The composite-layer semiconductor device is fabricated by depositing a gate on an n++ contact layer above a semi-insulating substrate. The semi-insulating substrate and gate are flipped onto an epoxy layer on the host substrate so that the gate is secured to the epoxy layer and the semi-insulating substrate presents an exposed backside. A portion of the exposed backside is removed. The source and drain ohmic contacts are applied to the exposed backside. The exposed backside is recessed at the central gate location to define the current path which connects the source and drain ohmic contacts.
摘要翻译：复合层半导体器件包括在主体衬底上方的栅极，栅极上方的n ++接触层以及施加到n ++接触层的源极和漏极欧姆接触。源极和漏极欧姆触点限定了通过n ++接触层向栅极凹陷的中心栅极位置。源极和漏极欧姆触点产生化学蚀刻的障碍，使得在中心栅极位置下方的电流路径可以以重复的步骤递增地凹入，以精确地定制用于耗尽或增强应用的器件的操作模式。通过在半绝缘基板上方的n ++接触层上沉积栅极来制造复合层半导体器件。半绝缘基板和栅极被翻转到主基板上的环氧树脂层上，使得栅极固定到环氧树脂层，半绝缘基板呈现暴露的背面。暴露背面的一部分被去除。源极和漏极欧姆接触应用于暴露的背面。暴露的背面凹陷在中央门位置以限定连接源极和漏极欧姆接触的电流路径。

7. 发明授权

US5219713A Multi-layer photoresist air bridge fabrication method 失效
标题翻译：多层光刻胶气桥制造方法
公开(公告)号：US5219713A
公开(公告)日：1993-06-15
申请号：US628816
申请日：1990-12-17
申请人： Gerald D. Robinson
发明人： Gerald D. Robinson
IPC分类号： G03F7/09 , H01L21/28 , H01L21/768 , H01L23/482 , H01L23/532
CPC分类号： G03F7/094 , H01L21/28 , H01L21/7682 , H01L21/76885 , H01L23/4821 , H01L23/53242 , H01L2924/0002
摘要： The method of constructing an air bridge on a substrate between spaced apart conductors on the substrate with the bridge spanning the distance between the conductors, by using PMGI to build a bridge pad on the substrate; using PMMA to build a bridge pattern over the pad with the ends of said conductors extending into said pattern; depositing titanium and gold over said pad within said pattern by directing the titanium and gold into said pattern onto said pad and conductor ends using relative motion between the substrate and the titanium and gold; and removing the PMGI and PMMA.
摘要翻译：通过使用PMGI在衬底上构建桥接焊盘，在衬底上的间隔开的导体之间的衬底上跨越导体之间的距离来构造空气桥的方法; 使用PMMA在所述焊盘上形成桥模式，所述导体的端部延伸到所述图案中; 通过在基底和钛和金之间的相对运动将钛和金沉积在所述图案中的所述垫上，通过将钛和金引导到所述图案中而进入所述垫和导体端; 并去除PMGI和PMMA。

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