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    • 8. 发明授权
    • System and method for handling interrupt and exception events in an
asymmetric multiprocessor architecture
    • 用于处理非对称多处理器架构中的中断和异常事件的系统和方法
    • US6003129A
    • 1999-12-14
    • US699294
    • 1996-08-19
    • Seungyeon Peter SongMoataz A. MohamedHeon-Chul ParkLe Nguyen
    • Seungyeon Peter SongMoataz A. MohamedHeon-Chul ParkLe Nguyen
    • G06F9/46G06F7/544G06F9/48G06F15/16G06F15/17G06F17/16G06F17/00
    • G06F7/5443G06F15/17
    • A multiprocessor computer system includes a plurality of processors, called asymmetric processors, having mutually dissimilar control and data-handling characteristics. The asymmetric processors are controlled by a single operating system although the individual processors have instruction sets that are mutually independent of the other processors. The multiprocessor computer system uses a multiprocessor architectural definition of interrupt and exception handling in which a processor, called a data or vector processor, having a large machine state and a large data width detects exceptions but defers interrupt and exception handling operations to another processor, called a control processor, having a small machine state and data width. The small machine state and small data width of the control processor are well suited for executing operating system programs such as interrupt and exception handling since control programs typically involve monitoring and control of individual flags and pointers. The data processor enters an idle state upon reset and when an exception is detected to facilitate system design and programming, and to simplify synchronization of the processors at system reset. A multiprocessor computer system includes a control processor which reads and writes control and status registers within a data processor. The control processor thus controls the operation of the data processor during execution of an operating system or application programs. The control processor has access to the control and status registers of the data processor independent of the data processor execution so that the same control and status registers may be accessed by the control processor and the data processor in parallel.
    • 多处理器计算机系统包括称为非对称处理器的多个处理器,具有相互不同的控制和数据处理特性。 非对称处理器由单个操作系统控制,尽管各个处理器具有彼此独立于其他处理器的指令集。 多处理器计算机系统使用中断和异常处理的多处理器体系结构定义,其中具有大机器状态和大数据宽度的称为数据或向量处理器的处理器检测异常,但是将中断和异常处理操作阻止到另一个处理器,称为 控制处理器,具有小的机器状态和数据宽度。 控制处理器的小机器状态和小数据宽度非常适合于执行诸如中断和异常处理之类的操作系统程序,因为控制程序通常涉及监视和控制各个标志和指针。 数据处理器在复位时进入空闲状态,并且当检测到异常以便于系统设计和编程时,并且在系统复位时简化处理器的同步。 多处理器计算机系统包括在数据处理器内读取和写入控制和状态寄存器的控制处理器。 因此,控制处理器在操作系统或应用程序的执行期间控制数据处理器的操作。 控制处理器可独立于数据处理器的执行访问数据处理器的控制和状态寄存器,使得控制处理器和数据处理器可以并行地访问相同的控制和状态寄存器。
    • 9. 发明申请
    • Superscalar RISC instruction scheduling
    • 超标量RISC指令调度
    • US20080059770A1
    • 2008-03-06
    • US11730566
    • 2007-04-02
    • Sanjiv GargKevin IadonatoLe NguyenJohannes Wang
    • Sanjiv GargKevin IadonatoLe NguyenJohannes Wang
    • G06F9/312
    • G06F9/3013G06F9/3824G06F9/3838G06F9/384G06F9/3855
    • A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
    • 一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统,适用于具有指令执行单元的计算机,该指令执行单元具有通过读地址端口访问的寄存器文件, 存储指令操作数。 包括数据相关性检查电路,用于确定指令之间的数据依赖性。 标签分配电路基于由数据相关性检查电路确定的数据依赖性,生成一个或多个标签以指定操作数的位置。 一组寄存器文件端口复用器选择标签分配电路产生的标签,并将标签传递到寄存器文件的读取地址端口,以存储执行结果。
    • 10. 发明申请
    • RISC microprocessor architecture implementing multiple typed register sets
    • RISC微处理器架构实现多种类型的寄存器集
    • US20070113047A1
    • 2007-05-17
    • US11651009
    • 2007-01-09
    • Sanjiv GargDerek LentzLe NguyenSho Chen
    • Sanjiv GargDerek LentzLe NguyenSho Chen
    • G06F15/76
    • G06F9/30029G06F9/30036G06F9/30112G06F9/30116G06F9/3012G06F9/30123G06F9/3013G06F9/30138G06F9/30167G06F9/30189G06F9/3851
    • A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean. comparisons without intervening conditional branch instructions, to minimize pipeline disruption.
    • 一种用于以多种模式操作的数据处理器的寄存器系统。 寄存器系统提供多个相同的寄存器组,数据处理器控制访问,使得指令和过程不需要指定任何给定的存储体。 整数寄存器集包括第一(RA [23:0])和第二(RA [31:24])子集和影子子集(RT [31:24])。 当数据处理器处于第一模式时,指令访问第一和第二子集。 当数据处理器处于第二模式时,指令可以访问第一子集,但是任何访问第二子集的尝试都被重新路由到阴影子集,而不是透明地指向该指令,从而允许系统例程看起来使用第二子集,而没有 必须保存和恢复哪个用户例程已写入第二个子集的数据。 重分类寄存器组分别提供整数宽度数据和浮点宽度数据,以响应整数指令和浮点指令。 布尔比较指令为要比较的源数​​据指定特定的整数或浮点寄存器,并为结果指定一个特定的布尔寄存器,因此没有专用的固定位置状态标志。 布尔组合指令组合指定的布尔寄存器,用于执行复杂布尔值。 比较没有干预条件分支指令,以最大限度地减少管道中断。