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    • 2. 发明申请
    • TRI-LAYER PLASMA ETCH RESIST REWORK
    • 三层等离子体蚀刻反应
    • US20090050604A1
    • 2009-02-26
    • US11843361
    • 2007-08-22
    • Jeannette Michelle JacquesYong Seok Choi
    • Jeannette Michelle JacquesYong Seok Choi
    • G03F1/00
    • H01L21/31144H01L21/02079H01L21/0271
    • Exemplary embodiments provide a tri-layer resist (TLR) stack used in a photolithographic process, and methods for resist reworking by a single plasma etch process. The single plasma etch process can be used to remove one or more portions/layers of the TLR stack that needs to be reworked in a single process. The removed portions/layers can then be re-formed and resulting in a reworked TLR stack for subsequent photo-resist (PR) processing. The disclosed plasma-etch resist rework method can be a fast, simple, and cost effective process used in either single or dual damascene tri-layer patterning processes for the fabrication of, for example, sub 45-nm node semiconductor structures.
    • 示例性实施例提供了在光刻工艺中使用的三层抗蚀剂(TLR)堆叠,以及通过单个等离子体蚀刻工艺来抵抗再加工的方法。 单个等离子体蚀刻工艺可用于去除在单个工艺中需要重新加工的TLR堆叠的一个或多个部分/层。 然后可以重新形成去除的部分/层,并导致用于随后的光致抗蚀剂(PR)处理的返工TLR堆叠。 所公开的等离子体蚀刻抗蚀剂返修方法可以是用于制造例如子45nm节点半导体结构的单镶嵌或双镶嵌三层图案化工艺中的快速,简单和成本有效的工艺。
    • 3. 发明授权
    • Tri-layer plasma etch resist rework
    • 三层等离子蚀刻抗蚀返修
    • US07811942B2
    • 2010-10-12
    • US11843361
    • 2007-08-22
    • Jeannette Michelle JacquesYong Seok Choi
    • Jeannette Michelle JacquesYong Seok Choi
    • H01L21/302H01L21/461
    • H01L21/31144H01L21/02079H01L21/0271
    • Exemplary embodiments provide a tri-layer resist (TLR) stack used in a photolithographic process, and methods for resist reworking by a single plasma etch process. The single plasma etch process can be used to remove one or more portions/layers of the TLR stack that needs to be reworked in a single process. The removed portions/layers can then be re-formed and resulting in a reworked TLR stack for subsequent photo-resist (PR) processing. The disclosed plasma-etch resist rework method can be a fast, simple, and cost effective process used in either single or dual damascene tri-layer patterning processes for the fabrication of, for example, sub 45-nm node semiconductor structures.
    • 示例性实施例提供了在光刻工艺中使用的三层抗蚀剂(TLR)堆叠,以及通过单个等离子体蚀刻工艺来抵抗再加工的方法。 单个等离子体蚀刻工艺可用于去除在单个工艺中需要重新加工的TLR堆叠的一个或多个部分/层。 然后可以重新形成去除的部分/层,并导致用于随后的光致抗蚀剂(PR)处理的返工TLR堆叠。 所公开的等离子体蚀刻抗蚀剂返修方法可以是用于制造例如子45nm节点半导体结构的单镶嵌或双镶嵌三层图案化工艺中的快速,简单和成本有效的工艺。