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1. 发明授权

US08004049B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08004049B2
公开(公告)日：2011-08-23
申请号：US11574478
申请日：2004-08-31
申请人： Jean-Michel Reynes , Stephane Alves , Ivana Deram , Blandino Lopes , Joel Margheritta , Frederico Morancho
发明人： Jean-Michel Reynes , Stephane Alves , Ivana Deram , Blandino Lopes , Joel Margheritta , Frederico Morancho
IPC分类号： H01L27/088
CPC分类号： H01L29/7802 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878
摘要： A device includes an array of cells, the source regions of the individual cells comprising a plurality of source region branches each extending towards a source region branch of an adjacent cell, the base regions of the individual cells comprising a corresponding plurality of base region branches merging together to form a single base region surrounding the source regions. The junctions between the merged base region and the drain region define rounded current conduction path areas for the on-state of the device between adjacent cells. Floating voltage regions of opposite conductivity type to the drain region are buried in the substrate beneath the merged base region. The features of the floating voltage regions define rings of the opposite conductivity type to the drain region that surround the current conduction paths of respective cells. The floating voltage regions include respective islands situated within the current conduction paths.
摘要翻译：一种设备包括单元阵列，各个单元的源区域包括多个源区域分支，每个源区域分支延伸到相邻单元的源区域分支，各个单元的基区包括对应的多个基本区域分支合并一起形成围绕源区域的单个碱基区域。合并的基极区域和漏极区域之间的结界定义用于相邻单元之间的器件的导通状态的圆形电流传导路径区域。与漏极区相反的导电类型的浮动电压区域埋在合并的基极区域下面的衬底中。浮动电压区域的特征限定环绕相应电池的电流传导路径的漏极区域的相反导电类型的环。浮置电压区域包括位于电流传导路径内的相应的岛。

2. 发明申请

US20090014792A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20090014792A1
公开(公告)日：2009-01-15
申请号：US11574478
申请日：2004-08-31
申请人： Jean-Michel Reynes , Stephane Alves , Ivana Deram , Blandino Lopes , Joel Margheritta , Frederic Morancho
发明人： Jean-Michel Reynes , Stephane Alves , Ivana Deram , Blandino Lopes , Joel Margheritta , Frederic Morancho
IPC分类号： H01L47/00
CPC分类号： H01L29/7802 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878
摘要： A power semiconductor device comprising an array of cells distributed over a surface of a substrate, the source regions of the individual cells of the array comprising a plurality of source region branches each extending laterally outwards towards at least one source region branch of an adjacent cell and presenting juxtaposed ends, the base regions of the individual cells of the array comprising a corresponding plurality of base region branches merging together adjacent and between the juxtaposed ends of the source region branches to form a single base region surrounding the source regions of the individual cells of the array in the substrate. The junctions between the merged base region and the drain region are solely concave laterally and define rounded current conduction path areas for the on-state of the device between adjacent cells that are depleted in the off-state of the device to block flow of current from the source regions to the drain electrode. Floating voltage regions of opposite conductivity type to the drain region are buried in the substrate beneath the merged base region and present features corresponding to and juxtaposed with features of the merged base region in each cell so that the voltage of the floating voltage regions tends to the voltage of the source regions when depletion layers blocking the current conduction paths reach the floating voltage regions, whereby to enhance the development of the depletion layers. The features of the floating voltage regions define rings of the opposite conductivity type to the drain region that surround the current conduction paths of respective cells. The floating voltage regions include respective islands situated within the current conduction paths.
摘要翻译：一种功率半导体器件，包括分布在衬底表面上的单元阵列，所述阵列的各个单元的源极区域包括多个源区域支路，每个源极区域分支向邻近小区的至少一个源极区域横向向外延伸，呈现并置的端部，阵列的各个单元的基极区域包括在源极区域的相邻端和并置端之间并联在一起的对应的多个基极区域分支，以形成围绕各个单元的源极区域的单个基极区域阵列在基片中。合并的基极区域和漏极区域之间的结点仅仅是侧向凹进的，并且限定用于在器件断开状态下耗尽的器件的导通状态的圆形电流传导路径区域，以阻止电流从源极区到漏电极。与漏极区相反的导电类型的浮动电压区域被埋在合并的基极区域下面的衬底中，并且呈现出与每个单元中合并的基极区域的特征对应并并置的特征，使得浮动电压区域的电压趋向于阻挡电流传导路径的耗尽层到达浮动电压区域时的源极区域的电压，从而增强耗尽层的发展。浮动电压区域的特征限定环绕相应电池的电流传导路径的漏极区域的相反导电类型的环。浮置电压区域包括位于电流传导路径内的相应的岛。

3. 发明授权

US07800135B2 Power semiconductor device and method of manufacturing a power semiconductor device 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US07800135B2
公开(公告)日：2010-09-21
申请号：US11996681
申请日：2005-07-25
申请人： Jean-Michel Reynes , Stephane Alves , Alain Deram , Blandino Lopes , Joel Margheritta
发明人： Jean-Michel Reynes , Stephane Alves , Alain Deram , Blandino Lopes , Joel Margheritta
IPC分类号： H01L29/74 , H01L21/8238
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/42368 , H01L29/66712 , H01L29/7811
摘要： A semiconductor power switch having an array of basic cells in which peripheral regions in the active drain region extend beside the perimeter of the base-drain junction, the peripheral regions being of higher dopant density than the rest of the second drain layer. Intermediate regions in the centre of the active drain region are provided of lighter dopant density than the rest of the second drain layer. This provides an improved compromise between the on-state resistance and the breakdown voltage by enlarging the current conduction path at in its active drain region. On the outer side of each edge cell of the array, the gate electrode extends over and beyond at least part of the perimeters of the base-source junction and the base-drain junction towards the adjacent edge of the die. Moreover, on the outer side of each edge cell, the second drain layer includes a region of reduced dopant density that extends beyond the gate electrode right to the adjacent edge of the die.
摘要翻译：一种具有碱性电池阵列的半导体功率开关，其中有源漏极区域中的外围区域延伸到基极 - 漏极结的周边之外，周边区域的掺杂剂密度高于第二漏极层的其余部分。有源漏极区域的中心的中间区域比第二漏极层的其余部分提供更轻的掺杂剂密度。这通过在其有源漏极区域中放大电流传导路径来提供导通状态电阻和击穿电压之间的改进的折衷。在阵列的每个边缘单元的外侧上，栅电极延伸超过基极 - 源极结和基极 - 漏极结的周边的至少一部分朝向裸片的相邻边缘。此外，在每个边缘电池的外侧，第二漏极层包括延伸超过栅电极直到模具的相邻边缘的掺杂剂浓度降低的区域。

4. 发明申请

US20080217657A1 Power Semiconductor Device and Method of Manufacturing a Power Semiconductor Device 有权
标题翻译：功率半导体器件及制造功率半导体器件的方法
公开(公告)号：US20080217657A1
公开(公告)日：2008-09-11
申请号：US11996681
申请日：2005-07-25
申请人： Jean-Michel Reynes , Stephane Alves , Alain Deram , Balandino Lopes , Joel Margheritta
发明人： Jean-Michel Reynes , Stephane Alves , Alain Deram , Balandino Lopes , Joel Margheritta
IPC分类号： H01L27/10 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/42368 , H01L29/66712 , H01L29/7811
摘要： A semiconductor power switch having an array of basic cells in which peripheral regions in the active drain region extend beside the perimeter of the base-drain junction, the peripheral regions being of higher dopant density than the rest of the second drain layer. Intermediate regions in the centre of the active drain region are provided of lighter dopant density than the rest of the second drain layer. This provides an improved compromise between the on-state resistance and the breakdown voltage by enlarging the current conduction path at in its active drain region. On the outer side of each edge cell of the array, the gate electrode extends over and beyond at least part of the perimeters of the base-source junction and the base-drain junction towards the adjacent edge of the die. Moreover, on the outer side of each edge cell, the second drain layer includes a region of reduced dopant density that extends beyond the gate electrode right to the adjacent edge of the die
摘要翻译：一种具有碱性电池阵列的半导体功率开关，其中有源漏极区域中的外围区域延伸到基极 - 漏极结的周边之外，周边区域的掺杂剂密度高于第二漏极层的其余部分。有源漏极区域的中心的中间区域比第二漏极层的其余部分提供更轻的掺杂剂密度。这通过在其有源漏极区域中放大电流传导路径来提供导通状态电阻和击穿电压之间的改进的折衷。在阵列的每个边缘单元的外侧上，栅电极延伸超过基极 - 源极结和基极 - 漏极结的周边的至少一部分朝向裸片的相邻边缘。此外，在每个边缘电池的外侧，第二漏极层包括减小的掺杂剂密度的区域，其延伸超过栅电极直到模具的相邻边缘

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