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1. 发明授权

US08604879B2 Matched feedback amplifier with improved linearity 有权
标题翻译：匹配反馈放大器具有提高的线性度
公开(公告)号：US08604879B2
公开(公告)日：2013-12-10
申请号：US13435455
申请日：2012-03-30
申请人： Jean-Marc Mourant , Feng-Jung Huang , Ran Li , Chuying Mao
发明人： Jean-Marc Mourant , Feng-Jung Huang , Ran Li , Chuying Mao
IPC分类号： H03F3/45 , H03F1/14
CPC分类号： H03F1/34 , H03F1/3211 , H03F3/45085 , H03F2203/45392
摘要： An impedance-matched amplifier utilizing a feed-forward linearization technique involving multiple negative feedbacks and distortion compensation without active tail current sources reduces noise, distortion, power consumption and heat dissipation requirements and increases linearity, dynamic range, signal-to-noise-ratio, sensitivity and quality of service. Some differential amplifier embodiments of the invention consume less than 2 mA at 5 Volts or 10 mW power consumption per 1 mW in peak and sustained output IP3 performance above 40 dBm. In contrast, for an input signal frequency of 200 MHz, a 16 dB gain state-of-the-art differential amplifier consumes 100 mA at 5 Volts with a peak output IP3 of 36 dBm while an implementation of a 16 dB gain differential amplifier embodying the invention consumes 77.7 mA at 5 Volts with a peak output IP3 of 46 dBm and sustained at or above 40 dBm over a wide frequency range.
摘要翻译：采用前馈线性化技术的阻抗匹配放大器，无需主动尾电流源就可以减少噪声，失真，功耗和散热要求，从而降低线性度，动态范围，信噪比，敏感度和服务质量。本发明的一些差分放大器实施例在峰值和持续输出IP3性能高于40dBm时以5伏特或每1mW的10mW功耗消耗小于2mA。相比之下，对于200 MHz的输入信号频率，16 dB增益最先进的差分放大器在5 V时消耗100 mA，峰值输出IP3为36 dBm，而16 dB增益差分放大器的实现体现在本发明在5伏特下消耗77.7mA，峰值输出IP3为46dBm，在宽频率范围内维持在40dBm以上。

2. 发明申请

US20130257537A1 MATCHED FEEDBACK AMPLIFIER WITH IMPROVED LINEARITY 有权
标题翻译：匹配的反馈放大器具有改进的线性
公开(公告)号：US20130257537A1
公开(公告)日：2013-10-03
申请号：US13435455
申请日：2012-03-30
申请人： Jean-Marc Mourant , Feng-Jung Huang , Ran Li , Chuying Mao
发明人： Jean-Marc Mourant , Feng-Jung Huang , Ran Li , Chuying Mao
IPC分类号： H03F3/45 , H03F1/34
CPC分类号： H03F1/34 , H03F1/3211 , H03F3/45085 , H03F2203/45392
摘要： An impedance-matched amplifier utilizing a feed-forward linearization technique involving multiple negative feedbacks and distortion compensation without active tail current sources reduces noise, distortion, power consumption and heat dissipation requirements and increases linearity, dynamic range, signal-to-noise-ratio, sensitivity and quality of service. Some differential amplifier embodiments of the invention consume less than 2 mA at 5 Volts or 10 mW power consumption per 1 mW in peak and sustained output IP3 performance above 40 dBm. In contrast, for an input signal frequency of 200 MHz, a 16 dB gain state-of-the-art differential amplifier consumes 100 mA at 5 Volts with a peak output IP3 of 36 dBm while an implementation of a 16 dB gain differential amplifier embodying the invention consumes 77.7 mA at 5 Volts with a peak output IP3 of 46 dBm and sustained at or above 40 dBm over a wide frequency range.
摘要翻译：采用前馈线性化技术的阻抗匹配放大器，无需主动尾电流源就可以减少噪声，失真，功耗和散热要求，从而降低线性度，动态范围，信噪比，敏感度和服务质量。本发明的一些差分放大器实施例在峰值和持续输出IP3性能高于40dBm时以5伏特或每1mW的10mW功耗消耗小于2mA。相比之下，对于200 MHz的输入信号频率，16 dB增益最先进的差分放大器在5 V时消耗100 mA，峰值输出IP3为36 dBm，而16 dB增益差分放大器的实现体现在本发明在5伏特下消耗77.7mA，峰值输出IP3为46dBm，在宽频率范围内维持在40dBm以上。

3. 发明授权

US10103690B2 Phase, amplitude and gate-bias optimizer for Doherty amplifier 有权
公开(公告)号：US10103690B2
公开(公告)日：2018-10-16
申请号：US15218539
申请日：2016-07-25
申请人： Naveen Yanduru , Chris Stephens , Jean-Marc Mourant , Chuying Mao
发明人： Naveen Yanduru , Chris Stephens , Jean-Marc Mourant , Chuying Mao
IPC分类号： H03F1/02 , H03F3/213 , H03F1/30 , H03F3/195
摘要： Systems, methods and instrumentalities are disclosed for Doherty amplifier optimization. Amplifier configurability and control therefore may be integrated. Amplitude alignment, phase alignment, amplifier gate biasing, driver gate biasing and temperature compensation for N paths in Doherty configurations may be integrated, for example, using a programmable LUT storing control bit patterns. Configurability may comprise reconfigurability between asymmetric power split ratios, between symmetric and asymmetric relationships and between classic and inverted phase relationships, permitting path reconfigurability for higher or lower power and leading or lagging phase. Multiple versions providing more or less configurability and/or control range with more or less insertion loss, such as design and production versions, may be pin compatible, e.g., to reduce time and expense for R&D and production transition. Integration of configurability and/or control may reduce complexity in design, development, control, optimization, production and application, e.g., by eliminating interfaces, mismatches or excessive capacitance between discrete chips.

4. 发明申请

US20180026583A1 PHASE, AMPLITUDE AND GATE-BIAS OPTIMIZER FOR DOHERTY AMPLIFIER 审中-公开
公开(公告)号：US20180026583A1
公开(公告)日：2018-01-25
申请号：US15218539
申请日：2016-07-25
申请人： Naveen Yanduru , Chris Stephens , Jean-Marc Mourant , Chuying Mao
发明人： Naveen Yanduru , Chris Stephens , Jean-Marc Mourant , Chuying Mao
IPC分类号： H03F1/02 , H03F3/213 , H03F1/30 , H03F3/195
CPC分类号： H03F1/0288 , H03F1/0261 , H03F1/301 , H03F3/195 , H03F3/213 , H03F2200/18 , H03F2200/192 , H03F2200/451
摘要： Systems, methods and instrumentalities are disclosed for Doherty amplifier optimization. Amplifier configurability and control therefore may be integrated. Amplitude alignment, phase alignment, amplifier gate biasing, driver gate biasing and temperature compensation for N paths in Doherty configurations may be integrated, for example, using a programmable LUT storing control bit patterns. Configurability may comprise reconfigurability between asymmetric power split ratios, between symmetric and asymmetric relationships and between classic and inverted phase relationships, permitting path reconfigurability for higher or lower power and leading or lagging phase. Multiple versions providing more or less configurability and/or control range with more or less insertion loss, such as design and production versions, may be pin compatible, e.g., to reduce time and expense for R&D and production transition. Integration of configurability and/or control may reduce complexity in design, development, control, optimization, production and application, e.g., by eliminating interfaces, mismatches or excessive capacitance between discrete chips.

5. 发明授权

US09853616B2 Low noise variable gain amplifier utilizing variable feedback techniques with constant input/output impedance 有权
公开(公告)号：US09853616B2
公开(公告)日：2017-12-26
申请号：US13870912
申请日：2013-04-25
申请人： Feng-Jung Huang , Jean-Marc Mourant
发明人： Feng-Jung Huang , Jean-Marc Mourant
IPC分类号： H03G3/30 , H03G1/00
CPC分类号： H03G1/0035 , H03G1/0023
摘要： Variable feedback architecture and control techniques for variable gain amplifiers (VGAs) concurrently maintain, across a wide range of VGA gain settings, minimal input and output impedance variations, a low noise figure, low rates of change in noise figure, high signal-to-noise ratio (SNR), high quality of service (QoS), low distortion, high and relatively constant output third order intercept point (i.e., IP3 or TOI). Variable feedback counteracts impedance variations caused by gain variations. Compared to conventional high performance VGAs, noise figure is lower (e.g. 3 dB lower at maximum gain and 12 dB lower at minimum gain) and relatively constant, IP3 is higher and relatively constant, small signal third order intermodulation signal (IM3) tone slope is relatively constant and input and output impedances are relatively constant. As gain decreases, the noise figure advantage is nearly dB per dB compared to conventional high performance VGAs.

6. 发明申请

US20140002282A1 HYBRID-CODING FOR IMPROVING TRANSIENT SWITCH RESPONSE IN A MULTI-CELL PROGRAMMABLE APPARATUS 有权
标题翻译：用于改进多小区可编程设备中的瞬态切换响应的混合编码
公开(公告)号：US20140002282A1
公开(公告)日：2014-01-02
申请号：US13539406
申请日：2012-06-30
申请人： Shawn Bawell , Jean-Marc Mourant , Feng-Jung Huang
发明人： Shawn Bawell , Jean-Marc Mourant , Feng-Jung Huang
IPC分类号： H03M7/00
CPC分类号： H03M7/00 , H03M7/165
摘要： Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.
摘要翻译：用于步进装置的混合编码，多小区架构和操作技术通过最小化或避免二进制编码步骤装置的瞬态响应中常见的毛刺，并通过最小化或避免显着增加或减少具有等效范围和分辨率的温度计编码步进装置所共有的一个或多个区域，封装尺寸，引脚数，功耗，插入损耗和寄生电容中的一个或多个劣化。

7. 发明授权

US08704684B2 Hybrid-coding for improving transient switch response in a multi-cell programmable apparatus 有权
标题翻译：用于改善多单元可编程装置中的瞬态开关响应的混合编码
公开(公告)号：US08704684B2
公开(公告)日：2014-04-22
申请号：US13539406
申请日：2012-06-30
申请人： Shawn Bawell , Jean-Marc Mourant , Feng-Jung Huang
发明人： Shawn Bawell , Jean-Marc Mourant , Feng-Jung Huang
IPC分类号： H03M7/00
CPC分类号： H03M7/00 , H03M7/165
摘要： Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.
摘要翻译：用于步进装置的混合编码，多小区架构和操作技术通过最小化或避免二进制编码步骤装置的瞬态响应中常见的毛刺，并通过最小化或避免显着增加或减少具有等效范围和分辨率的温度计编码步进装置所共有的一个或多个区域，封装尺寸，引脚数，功耗，插入损耗和寄生电容中的一个或多个劣化。

8. 发明申请

US20120242408A1 LOW NOISE VARIABLE GAIN AMPLIFIER UTILIZING VARIABLE FEEDBACK TECHNIQUES WITH CONSTANT INPUT/OUTPUT IMPEDANCE 有权
标题翻译：低噪声可变增益放大器利用具有恒定输入/输出阻抗的可变反馈技术
公开(公告)号：US20120242408A1
公开(公告)日：2012-09-27
申请号：US13193604
申请日：2011-07-29
申请人： Feng-Jung Huang , Jean-Marc Mourant
发明人： Feng-Jung Huang , Jean-Marc Mourant
IPC分类号： H03G3/30 , H03F3/45
CPC分类号： H03F1/34 , H03F3/45098 , H03F2200/144 , H03F2203/45338 , H03F2203/45372 , H03F2203/45466 , H03F2203/45494 , H03G1/0017 , H03G1/0023 , H03G1/0082 , H03G1/0088
摘要： Variable feedback architecture and control techniques for variable gain amplifiers (VGAs) concurrently maintain, across a wide range of VGA gain settings, minimal input and output impedance variations, a low noise figure, low rates of change in noise figure, high signal-to-noise ratio (SNR), high quality of service (QoS), low distortion, high and relatively constant output third order intercept point (i.e., IP3 or TOI). Variable feedback counteracts impedance variations caused by gain variations. Compared to conventional high performance VGAs, noise figure is lower (e.g. 3 dB lower at maximum gain and 12 dB lower at minimum gain) and relatively constant, IP3 is higher and relatively constant, small signal third order intermodulation signal (IM3) tone slope is relatively constant and input and output impedances are relatively constant. As gain decreases, the noise figure advantage is nearly dB per dB compared to conventional high performance VGAs.
摘要翻译：可变增益放大器（VGA）的可变反馈架构和控制技术在广泛的VGA增益设置下同时保持最小的输入和输出阻抗变化，低噪声系数，低噪声系数变化率，高信噪比，噪声比（SNR），高服务质量（QoS），低失真，高和相对恒定的输出三阶截点（即IP3或TOI）。可变反馈抵消由增益变化引起的阻抗变化。与常规高性能VGA相比，噪声系数较低（例如，最大增益下降3 dB，最小增益降低12 dB），相对恒定，IP3较高且相对恒定，小信号三阶互调信号（IM3）色调斜率为相对恒定，输入和输出阻抗相对恒定。随着增益的降低，与传统的高性能VGA相比，噪声系数优势几乎达到每dB dB。

9. 发明申请

US20160241216A1 MULTI-BIT CELL ATTENUATOR 审中-公开
标题翻译：多位细胞衰减器
公开(公告)号：US20160241216A1
公开(公告)日：2016-08-18
申请号：US15136962
申请日：2016-04-24
申请人： SHAWN BAWELL , Jean-Marc Mourant , Feng-Jung Huang
发明人： SHAWN BAWELL , Jean-Marc Mourant , Feng-Jung Huang
IPC分类号： H03H11/24 , H03G1/00
摘要： Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.
摘要翻译：用于步进装置的混合编码，多小区架构和操作技术通过最小化或避免二进制编码步骤装置的瞬态响应中常见的毛刺，并通过最小化或避免显着增加或减少具有等效范围和分辨率的温度计编码步进装置所共有的一个或多个区域，封装尺寸，引脚数，功耗，插入损耗和寄生电容中的一个或多个劣化。

10. 发明申请

US20140320207A1 LOW NOISE VARIABLE GAIN AMPLIFIER UTILIZING VARIABLE FEEDBACK TECHNIQUES WITH CONSTANT INPUT/OUTPUT IMPEDANCE 有权
标题翻译：低噪声可变增益放大器利用具有恒定输入/输出阻抗的可变反馈技术
公开(公告)号：US20140320207A1
公开(公告)日：2014-10-30
申请号：US13870912
申请日：2013-04-25
申请人： Feng-Jung Huang , Jean-Marc Mourant
发明人： Feng-Jung Huang , Jean-Marc Mourant
IPC分类号： H03G3/00
CPC分类号： H03G1/0035 , H03G1/0023
摘要： Variable feedback architecture and control techniques for variable gain amplifiers (VGAs) concurrently maintain, across a wide range of VGA gain settings, minimal input and output impedance variations, a low noise figure, low rates of change in noise figure, high signal-to-noise ratio (SNR), high quality of service (QoS), low distortion, high and relatively constant output third order intercept point (i.e., IP3 or TOI). Variable feedback counteracts impedance variations caused by gain variations. Compared to conventional high performance VGAs, noise figure is lower (e.g. 3 dB lower at maximum gain and 12 dB lower at minimum gain) and relatively constant, IP3 is higher and relatively constant, small signal third order intermodulation signal (IM3) tone slope is relatively constant and input and output impedances are relatively constant. As gain decreases, the noise figure advantage is nearly dB per dB compared to conventional high performance VGAs.
摘要翻译：可变增益放大器（VGA）的可变反馈架构和控制技术在广泛的VGA增益设置下同时保持最小的输入和输出阻抗变化，低噪声系数，低噪声系数变化率，高信噪比，噪声比（SNR），高服务质量（QoS），低失真，高和相对恒定的输出三阶截点（即IP3或TOI）。可变反馈抵消由增益变化引起的阻抗变化。与常规高性能VGA相比，噪声系数较低（例如，最大增益下降3 dB，最小增益降低12 dB），相对恒定，IP3较高且相对恒定，小信号三阶互调信号（IM3）色调斜率为相对恒定，输入和输出阻抗相对恒定。随着增益的降低，与传统的高性能VGA相比，噪声系数优势几乎达到每dB dB。

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