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    • 6. 发明申请
    • METHOD FOR MANUFACTURING A SIGNAL LINE, THIN FILM TRANSISTOR PANEL, AND METHOD FOR MANUFACTURING THE THIN FILM TRANSISTOR PANEL
    • 用于制造信号线,薄膜晶体管板的方法和制造薄膜晶体管板的方法
    • US20080203390A1
    • 2008-08-28
    • US11932233
    • 2007-10-31
    • Do-Hyun KimWon-Suk ShinChang-Oh JeongHong-Sick ParkEun-Guk LeeJe-Hun Lee
    • Do-Hyun KimWon-Suk ShinChang-Oh JeongHong-Sick ParkEun-Guk LeeJe-Hun Lee
    • H01L29/49H01L21/44H01L21/84
    • H01L27/12H01L27/124H01L27/1288H01L29/458
    • A method for manufacturing a thin film transistor array panel includes forming a gate line on a substrate; sequentially forming a gate insulating layer, a silicon layer, and a conductor layer including a lower layer and an upper layer on the gate line, forming a photoresist film, on the conductor layer, patterning the photoresist film to form a photoresist pattern including a first portion and a second portion having a greater thickness than the first portion, etching the upper layer and the lower layer by using the photoresist pattern as art etch mask, etching the silicon layer by using the photoresist pattern as an etch mask to form a semiconductor, removing the second portion of the photoresist pattern by using an etch back process, selectively wet-etching the upper layer of the conductor layer by using the photoresist pattern as an etch mask, dry-etching the lower layer of the conductor layer by using the photoresist pattern as an etch mask to form a data line and a drain electrode including remaining upper and lower layers, and forming a pixel electrode connected to the drain electrode.
    • 一种制造薄膜晶体管阵列面板的方法,包括在基板上形成栅极线; 在栅极线上顺序地形成栅极绝缘层,硅层和包括下层和上层的导体层,在导体层上形成光致抗蚀剂膜,图案化光致抗蚀剂膜以形成包括第一 部分和第二部分具有比第一部分更大的厚度,通过使用光致抗蚀剂图案作为蚀刻掩模蚀刻上层和下层,通过使用光致抗蚀剂图案作为蚀刻掩模来蚀刻硅层以形成半导体, 通过使用回蚀工艺去除光致抗蚀剂图案的第二部分,通过使用光致抗蚀剂图案作为蚀刻掩模来选择性地湿法蚀刻导体层的上层,通过使用光致抗蚀剂干蚀刻导体层的下层 图案作为蚀刻掩模以形成包括剩余的上层和下层的数据线和漏极,并且形成连接到漏电极的像素电极 。
    • 8. 发明授权
    • Thin film transistor array panel and manufacturing method thereof
    • 薄膜晶体管阵列面板及其制造方法
    • US07863607B2
    • 2011-01-04
    • US11980871
    • 2007-10-30
    • Je-Hun LeeDo-Hyun KimChang-Oh Jeong
    • Je-Hun LeeDo-Hyun KimChang-Oh Jeong
    • H01L29/786
    • H01L29/7869H01L27/1225
    • The disclosed thin film transistor array panel includes an insulating substrate, a channel layer including an oxide formed on the insulating substrate. A gate insulating is layer formed on the channel layer and a gate electrode is formed on the gate insulating layer. An interlayer insulating layer is formed on the gate electrode and a data line formed on the interlayer insulating layer and includes a source electrode, wherein the data line is made of a first conductive layer and a second conductive layer. A drain electrode formed on the interlayer insulating layer, and includes the first conductive layer and the second conductive layer. A pixel electrode extends from the first conductive layer of the drain electrode and a passivation layer formed on the data line and the drain electrode. A spacer formed on the passivation layer.
    • 所公开的薄膜晶体管阵列面板包括绝缘基板,包括形成在绝缘基板上的氧化物的沟道层。 栅极绝缘层是在沟道层上形成的层,栅电极形成在栅极绝缘层上。 在栅电极上形成层间绝缘层,形成在层间绝缘层上的数据线,包括源电极,其中数据线由第一导电层和第二导电层构成。 一种形成在层间绝缘层上的漏极,包括第一导电层和第二导电层。 像素电极从漏电极的第一导电层和形成在数据线和漏电极上的钝化层延伸。 形成在钝化层上的间隔物。