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1. 发明申请

US20060107144A1 Power reduction in module-based scan testing 审中-公开
标题翻译：基于模块的扫描测试功耗降低
公开(公告)号：US20060107144A1
公开(公告)日：2006-05-18
申请号：US11305581
申请日：2005-12-16
申请人： Jayashree Saxena , Kenneth Butler , Atul Jain , Anthony Fryars , Graham Hetherington
发明人： Jayashree Saxena , Kenneth Butler , Atul Jain , Anthony Fryars , Graham Hetherington
IPC分类号： G01R31/28
CPC分类号： G01R31/318577 , G01R31/31721
摘要： A circuit and method for reducing the power consumed by module-based scan testing. In one embodiment constant data is provided to inputs, such as 33, of scan chains not used in testing, such as 32. Another embodiment is a method whereby transitions in a subset of scan chains, such as 32, are minimized through the use of constant input data.
摘要翻译：用于减少基于模块的扫描测试消耗的功率的电路和方法。在一个实施例中，恒定数据被提供给输入，例如33，未在测试中使用的扫描链，例如32。另一个实施例是通过使用恒定输入数据来最小化扫描链子集（诸如32）中的转变的方法。

2. 发明申请

US20080235545A1 Re-using production test scan paths for system test of an integrated circuit 审中-公开
标题翻译：重新使用生产测试扫描路径进行集成电路的系统测试
公开(公告)号：US20080235545A1
公开(公告)日：2008-09-25
申请号：US12074722
申请日：2008-03-05
申请人： Vinay Burjinroppa Jayaram , Anthony Fryars
发明人： Vinay Burjinroppa Jayaram , Anthony Fryars
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318552 , G01R31/318547
摘要： Mission circuitry provided to implement desired data processing operations in an integrated circuit apparatus is tested by using a plurality of scan paths to subject the mission circuitry to production testing before the integrated circuit apparatus is deployed in a mission environment. The plurality of scan paths are re-used to subject the mission circuitry to further testing while the integrated circuit apparatus is deployed in a mission environment.
摘要翻译：提供用于在集成电路装置中实现所需数据处理操作的任务电路通过使用多个扫描路径进行测试，以在集成电路设备部署在任务环境中之前对任务电路进行生产测试。当集成电路设备部署在任务环境中时，多个扫描路径被重新用于使任务电路进一步测试。

3. 发明授权

US06654920B1 LBIST controller circuits, systems, and methods with automated maximum scan channel length 有权
标题翻译： LBIST控制器电路，系统和方法具有自动最大扫描通道长度
公开(公告)号：US06654920B1
公开(公告)日：2003-11-25
申请号：US09696326
申请日：2000-10-25
申请人： Graham G. Hetherington , Anthony Fryars
发明人： Graham G. Hetherington , Anthony Fryars
IPC分类号： G01R3128
CPC分类号： G01R31/318555
摘要： An integrated circuit (10) comprising combinational circuitry (13). The integrated circuit further comprises a plurality of scan channels (SC1 through SC4). Each of the plurality of scan channels comprises a number of scan elements (EC11 through EC45). For any of the plurality of scan channels having a number of scan elements greater than one element, the scan channel comprises a first element in the scan channel and a last element in the scan channel. For any of the plurality of scan channels having a number of scan elements equal to one element, the one element is both a first element and a last element in the scan channel. Further, selected ones of the scan elements are coupled to affect operation of the combinational circuitry. The integrated circuit further comprises circuitry (24) for coupling a predetermined pattern into the first element of each of the plurality of scan channels and circuitry (26) for detecting the predetermined pattern in the last element of each of the plurality scan channels. Finally, the integrated circuit further comprises circuitry (22, 23) for determining, in response to circuitry for detecting, the number of scan elements in a longest of the plurality of scan channels.
摘要翻译：一种包括组合电路（13）的集成电路（10）。集成电路还包括多个扫描通道（SC1至SC4）。多个扫描通道中的每一个包括多个扫描元件（EC11至EC45）。对于具有大于一个元件的多个扫描元件的多个扫描通道中的任何一个，扫描通道包括扫描通道中的第一元件和扫描通道中的最后一个元件。对于具有等于一个元件的多个扫描元件的多个扫描通道中的任何一个，该一个元件都是扫描通道中的第一元件和最后一个元件。此外，选择的扫描元件被耦合以影响组合电路的操作。集成电路还包括用于将预定图案耦合到多个扫描通道中的每一个的第一元件的电路（24）和用于检测多个扫描通道中每个扫描通道的最后一个元件中的预定图案的电路（26）。最后，集成电路还包括电路（22,23），用于响应于用于检测多个扫描通道中最长的扫描信道中的扫描元件的数量来确定。

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