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1. 发明授权

US5283323A Method of producing immune response 失效
标题翻译：产生免疫反应的方法
公开(公告)号：US5283323A
公开(公告)日：1994-02-01
申请号：US715712
申请日：1991-06-18
申请人： Jay A. Berzofsky , Hajime Kawamura
发明人： Jay A. Berzofsky , Hajime Kawamura
IPC分类号： A61K39/00 , A61K47/48 , C07K14/47 , C07K14/805 , C07K16/42 , C07K13/00
CPC分类号： C07K16/4283 , A61K47/4833 , C07K14/47 , C07K14/805 , A61K39/00
摘要： The present invention discloses a process for enhancing antibody response to an antigen. A novel step in the process is the preparation of a conjugate of the antigen with an anti-immunoglobulin. The conjugate thus prepared is then administered to a host for in vivo effect or presented to T and B cells in a suitable culture system for in vitro response. The present invention by increasing immunogenicity makes it possible to produce antibodies against very low doses of antigens and otherwise weak or insufficient antigens or synthetic vaccines.
摘要翻译：本发明公开了一种增强对抗原的抗体应答的方法。该方法的新颖步骤是制备抗原与抗免疫球蛋白的缀合物。然后将如此制备的缀合物施用于宿主用于体内效应，或者在合适的培养系统中呈递给T细胞和B细胞用于体外应答。本发明通过增加免疫原性使得可以产生针对非常低剂量的抗原的抗体，否则产生弱或不足的抗原或合成疫苗。

2. 发明授权

US5130974A Multidrop control network commonly used for carrying network management signals and topology reconfiguration signals 失效
标题翻译：多点控制网络通常用于承载网络管理信号和拓扑重构信号
公开(公告)号：US5130974A
公开(公告)日：1992-07-14
申请号：US501804
申请日：1990-03-30
申请人： Hajime Kawamura , Keisuke Kuroyanagi
发明人： Hajime Kawamura , Keisuke Kuroyanagi
IPC分类号： H04L29/14 , H04J3/08 , H04L12/24
CPC分类号： H04L41/0816 , H04J3/085 , H04L41/0677
摘要： A data communication system comprises a network management center and switching nodes which are interconnected by regular and spare routes. Each of the regular and spare routes comprises data channels and a control chnanel, the data channels of the regular routes forming a data network for carrying signals to and from user terminals and the control channel of each regular or spare route is connected to the control channels of other regular or spare routes to form a control network of multidrop structure for carrying a network management signal from the center to the nodes as well as network response signals from the nodes to the center. Each of the nodes transmits a request signal through the control network in the event of a line fault in the transmission lines to request permission to establish a new regular route to an adjacent node and transmits a grant signal through the control network in response to receipt of a request signal from an adjacent node indicating that the request is granted if an alternate route is available. The control network is dynamically reconfigured in accordance with the presence and absence of the request signal and the grant signal received from adjacent nodes.
摘要翻译：数据通信系统包括通过常规和备用路由互连的网络管理中心和交换节点。常规路由和备用路由中的每一条包括数据信道和控制信道，形成用于向用户终端和从用户终端传送信号的数据网络的常规路由的数据信道和每个常规或备用路由的控制信道连接到控制信道形成其他常规或备用路由，形成多中心结构的控制网络，用于承载中心到节点的网络管理信号，以及从节点到中心的网络响应信号。每个节点在传输线中发生线路故障的情况下通过控制网络发送请求信号，以请求建立到相邻节点的新规则路由的许可，并响应于接收到的信息而通过控制网络发送授权信号来自相邻节点的请求信号，指示如果备用路由可用则该请求被授权。控制网络根据请求信号的存在和不存在以及从相邻节点接收到的授权信号进行动态重新配置。

3. 发明授权

US5343466A Path routing system for communication network 失效
标题翻译：通信网路径路由系统
公开(公告)号：US5343466A
公开(公告)日：1994-08-30
申请号：US20332
申请日：1993-02-19
申请人： Hajime Kawamura
发明人： Hajime Kawamura
IPC分类号： H04L12/725 , H04L12/751 , H04L12/56
CPC分类号： H04L45/00 , H04L45/26
摘要： In a path routing system for a communication network having a plurality of nodes and a plurality of transmission lines, an originate node transmits a routing message with a transmission line attribute designation to a bypass node for establishing a path between the originate node and a terminal node. A repeater node searches for a transmission line having the same attribute as the transmission line attribute designation upon receipt of the routing message with the transmission line attribute designation, and transmits the message to an adjacent node through the searched transmission line. A path between the originate node and the terminal node is autonomously selected to pass through transmission lines having the desired attribute by repeatably searching the transmission lines and transmitting the message between nodes disposed between the originate node and the terminal node.
摘要翻译：在具有多个节点和多个传输线的通信网络的路径路由系统中，起始节点向旁路节点发送具有传输线属性指定的路由消息，用于建立起始节点和终端节点之间的路径。中继器节点在接收到具有传输线属性指定的路由消息时，搜索具有与传输线属性指定相同属性的传输线，并通过所搜索的传输线将消息发送到相邻节点。原始节点和终端节点之间的路径被自主选择，以通过可重复地搜索传输线并在布置在起始节点和终端节点之间的节点之间传送消息来通过具有期望属性的传输线。

4. 发明申请

US20090140769A1 System-in-package 审中-公开
标题翻译：系统级封装
公开(公告)号：US20090140769A1
公开(公告)日：2009-06-04
申请号：US12289822
申请日：2008-11-05
申请人： Katsunobu Suzuki , Takao Ikeuchi , Fumihiko Tajima , Kazuaki Maehara , Hajime Kawamura , Makoto Wakasugi
发明人： Katsunobu Suzuki , Takao Ikeuchi , Fumihiko Tajima , Kazuaki Maehara , Hajime Kawamura , Makoto Wakasugi
IPC分类号： H03K19/0175
CPC分类号： H01L25/18 , H01L23/3677 , H01L23/49827 , H01L23/5386 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2225/06506 , H01L2225/0651 , H01L2924/00014 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A System-in-Package includes a first chip to be mounted in common for a plurality of product types, a second chip having different specifications for each product type, and a wiring substrate being common to a plurality of product types, on which the first chip and the second chip are to be mounted. A setting signal is supplied from the second chip to the first chip.
摘要翻译：一种系统级封装包括：为多种产品类型共同安装的第一芯片;对于每种产品类型具有不同规格的第二芯片;以及多个产品类型共有的布线基板，芯片和第二芯片将被安装。设置信号从第二芯片提供给第一芯片。

5. 发明授权

US5757775A Interface for detecting loss of call setup ATM cell to prevent misrouting in destination local network 失效
标题翻译：用于检测呼叫建立丢失的ATM信元的接口，以防止目的本地网络中的错误路由
公开(公告)号：US5757775A
公开(公告)日：1998-05-26
申请号：US665097
申请日：1996-06-14
申请人： Masaru Yokoyama , Hajime Kawamura
发明人： Masaru Yokoyama , Hajime Kawamura
IPC分类号： H04Q3/00 , H04L12/70 , H04L12/801 , H04L12/911 , H04L12/951 , H04Q3/58 , H04Q11/04 , H04J3/14
CPC分类号： H04Q11/0478 , H04L2012/5615 , H04L2012/563 , H04L2012/5652
摘要： An interface between an ATM network and a local network includes a cell disassembler for disassembling ATM cells from the ATM network and transmitting a disassembled signal to the local network. A cell assembler assembles a signal from the local network into ATM cells and transmitting the ATM cells to the ATM network. A cell loss detector is provided for detecting a loss of a cell in a series of ATM cells from the ATM network. A signaling cell detector detects a call setup ATM cell from the ATM network. A coincidence gate produces an output when there is a coincidence between the detection of the cell loss and the detection of the call setup ATM cell. When the coincidence is detected, a busy tone is supplied to the cell assembler, where it is assembled into ATM cells and transmitted to the ATM network.
摘要翻译： ATM网络和本地网络之间的接口包括用于从ATM网络中拆卸ATM信元并将分解的信号发送到本地网络的信元分解器。信元汇编器将来自本地网络的信号组合成ATM信元，并将ATM信元发送到ATM网络。提供一种用于检测来自ATM网络的一系列ATM信元中的小区的丢失的信元丢失检测器。信令小区检测器从ATM网络检测呼叫建立ATM信元。当检测到信元丢失和呼叫建立ATM信元的检测出现一致时，符合门产生输出。当检测到符合时，向单元汇编器提供忙音，其中它被组合成ATM信元并被发送到ATM网络。

6. 发明授权

US5801956A Method for deciding the feasibility of logic circuit prior to performing logic synthesis 失效
标题翻译：在执行逻辑合成之前决定逻辑电路的可行性的方法
公开(公告)号：US5801956A
公开(公告)日：1998-09-01
申请号：US667334
申请日：1996-06-20
申请人： Hajime Kawamura , Takeharu Nemoto , Takuo Nakaki
发明人： Hajime Kawamura , Takeharu Nemoto , Takuo Nakaki
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A logic circuit design procedure comprises a step of deciding the feasibility of hardware after HDL description and functional verification, and a step of performing logic synthesis of the HDL description which has been determined to be feasible. The feasibility decision step comprises at least a decision on the possibility of spike transfer and a decision on oscillation. The spike transfer check step determines whether at least one of a clock signal and a reset signal of any sequential circuit is output from a combinational circuit. The oscillation check step determines whether an output signal of any combinational circuit is recursively input thereto without passing through a sequential circuit. Only the HDL description which passes the feasibility test is allowed to enter the logic synthesis stage.
摘要翻译：逻辑电路设计程序包括在HDL描述和功能验证之后决定硬件的可行性的步骤，以及执行已被确定为可行的HDL描述的逻辑合成步骤。可行性决定步骤至少包括关于峰值转移和振荡决定的可能性的决定。尖峰传输检查步骤确定是否从组合电路输出任何时序电路的时钟信号和复位信号中的至少一个。振荡检查步骤确定任何组合电路的输出信号是否被递归地输入到其中，而不经过顺序电路。通过可行性测试的HDL描述只允许进入逻辑合成阶段。

7. 发明授权

US5500862A Multi-layer digital circuit board with a test pattern section 失效
标题翻译：具有测试图案部分的多层数字电路板
公开(公告)号：US5500862A
公开(公告)日：1996-03-19
申请号：US331174
申请日：1994-10-28
申请人： Hajime Kawamura
发明人： Hajime Kawamura
IPC分类号： G01R31/28 , G01R31/3185 , H05K1/02 , H05K1/18 , H04B17/00
CPC分类号： G01R31/3185 , H05K1/0268 , H05K1/181
摘要： In a digital circuit board comprising a circuit mounting section and a test pattern section, the circuit mounting section has a circuit upper face on which the edge connector and an LSI circuit are mounted. The circuit mounting section has a circuit back face opposite to the circuit upper face. The circuit mounting section has a plurality of terminal through holes, the connector terminals including connector test terminals for use in testing the LSI circuit, and the LSI terminals including LSI test terminals for use in testing the LSI circuit. The terminal through holes have ends connected to the connector test terminals and to the LSI test terminals and have another ends which reach to the circuit back face. The test pattern section has a test upper face which is in contact with the circuit back face and on which test conductive patterns are formed. The test conductive patterns are for use in testing the LSI circuit and connecting the LSI test terminals with the connector test terminals via the terminal through holes. A plurality of LSI circuits may be mounted on the digital circuit board. In the event, the LSI circuit may be both a boundary scan LSI with a boundary scan test logic circuit and an unboundary scan LSI which does not contain the boundary scan test logic circuit.
摘要翻译：在包括电路安装部分和测试图形部分的数字电路板中，电路安装部分具有安装边缘连接器和LSI电路的电路上表面。电路安装部具有与电路上表面相对的电路背面。电路安装部分具有多个端子通孔，连接器端子包括用于测试LSI电路的连接器测试端子，以及包括用于测试LSI电路的LSI测试端子的LSI端子。端子通孔的端部连接到连接器测试端子和LSI测试端子，并且具有到达电路背面的另一端。测试图形部分具有与电路背面接触并且在其上形成测试导电图案的测试上表面。测试导电图案用于测试LSI电路，并通过端子通孔将LSI测试端子与连接器测试端子连接。多个LSI电路可以安装在数字电路板上。在这种情况下，LSI电路可以是具有边界扫描测试逻辑电路的边界扫描LSI和不包含边界扫描测试逻辑电路的无边界扫描LSI。

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