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1. 发明授权

US07088123B1 System and method for extraction of C-V characteristics of ultra-thin oxides 有权
标题翻译：提取超薄氧化物C-V特性的系统和方法
公开(公告)号：US07088123B1
公开(公告)日：2006-08-08
申请号：US11217144
申请日：2005-08-31
申请人： Jau-Yuann Yang , Hamseswari Renganathan , Kaiping Liu , Antonio Luis Pacheco Rotondaro
发明人： Jau-Yuann Yang , Hamseswari Renganathan , Kaiping Liu , Antonio Luis Pacheco Rotondaro
IPC分类号： G01R31/02
CPC分类号： G01R31/2601 , G01R31/2648 , G01R31/2839
摘要： In one embodiment, a method for extracting C-V characteristics of ultra-thin oxides includes coupling a device under test to a testing structure, in which the device under test includes a plurality of transistors. Alternatively, the device under test includes a plurality of varactors. The method further includes inputting a radio frequency signal of at least one GHz into the testing structure, de-embedding the parasitics of the testing structure, inputting a bias into the device under test, determining the capacitance density per gate width of the device under test, plotting capacitance density per gate width versus gate length to obtain a first curve, and determining a slope of the first curve. These steps are repeated for one or more additional biasing conditions, and the determined slopes are plotted on a capacitance density per voltage graph to obtain a C-V curve for the device under test.
摘要翻译：在一个实施例中，一种用于提取超薄氧化物的C-V特性的方法包括将被测试器件耦合到测试结构，其中被测器件包括多个晶体管。或者，被测器件包括多个变容二极管。该方法还包括将至少一GHz的射频信号输入到测试结构中，解嵌入测试结构的寄生效应，将偏置输入到被测器件中，确定被测器件的每个门宽的电容密度绘制每个栅极宽度对栅极长度的电容密度以获得第一曲线，并且确定第一曲线的斜率。对于一个或多个附加偏置条件重复这些步骤，并且将确定的斜率绘制在每个电压图上的电容密度上，以获得被测器件的C-V曲线。

2. 发明授权

US07691714B2 Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor 有权
标题翻译：具有位于由源/漏区产生的边界内的位错环的半导体器件及其制造方法
公开(公告)号：US07691714B2
公开(公告)日：2010-04-06
申请号：US11042415
申请日：2005-01-25
申请人： Antonio Luis Pacheco Rotondaro , Kaiping Liu , Jihong Chen , Amitabh Jain
发明人： Antonio Luis Pacheco Rotondaro , Kaiping Liu , Jihong Chen , Amitabh Jain
IPC分类号： H01L21/336 , H01L21/337
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/823814 , H01L21/823871
摘要： The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.
摘要翻译：本发明提供了晶体管器件的制造方法，集成电路的制造方法以及晶体管器件。制造晶体管器件的方法以及其他步骤包括在衬底上形成栅极结构，并在栅极结构附近形成衬底中的源极/漏极区域，源极/漏极区域具有与衬底形成电连接的边界。该方法还包括在衬底中形成位错环，位错环不延伸到源/漏区的边界之外。

3. 发明授权

US07118979B2 Method of manufacturing transistor having germanium implant region on the sidewalls of the polysilicon gate electrode 有权
标题翻译：在多晶硅栅电极的侧壁上制造具有锗注入区的晶体管的方法
公开(公告)号：US07118979B2
公开(公告)日：2006-10-10
申请号：US10701818
申请日：2003-11-05
申请人： Kaiping Liu , Zhiqiang Wu , Majid Movahed Mansoorz
发明人： Kaiping Liu , Zhiqiang Wu , Majid Movahed Mansoorz
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/26506 , H01L21/26586 , H01L21/2807 , H01L21/28105 , H01L21/823828
摘要： The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.
摘要翻译：本发明提供一种具有位于其中的锗注入区域170的晶体管100及其制造方法，以及包括上述晶体管的集成电路。在一个实施例中，晶体管100包括位于半导体衬底110上方的多晶硅栅电极140，其中多晶硅栅电极140的侧壁上具有锗注入区170。晶体管100还包括靠近多晶硅栅电极140位于半导体衬底110内的源/漏区160。

4. 发明授权

US06727131B2 System and method for addressing junction capacitances in semiconductor devices 有权
标题翻译：用于解决半导体器件中的结电容的系统和方法
公开(公告)号：US06727131B2
公开(公告)日：2004-04-27
申请号：US10279650
申请日：2002-10-24
申请人： Zhiqiang Wu , Kaiping Liu
发明人： Zhiqiang Wu , Kaiping Liu
IPC分类号： H01L218238
CPC分类号： H01L21/26513 , H01L21/324 , H01L29/6659
摘要： A method of forming a semiconductor device is provided that comprises forming a gate conductor proximate to and insulated from an outer surface of a semiconductor substrate. The gate conductor defines a channel region disposed inwardly from the gate conductor. Source and drain regions are formed in the semiconductor substrate, each disposed adjacent one edge of the channel region. The semiconductor substrate and the source and drain regions have an associated bottom wall junction capacitance. A transient enhanced diffusion anneal is used to affect ion concentration profiles associated with the source and drain regions, resulting in an increased balance in the ion concentration profiles of the source and drain regions and an ion concentration associated with the semiconductor substrate, which results in reduction of the bottom wall junction capacitance.
摘要翻译：提供一种形成半导体器件的方法，其包括形成靠近并与半导体衬底的外表面绝缘的栅极导体。栅极导体限定了从栅极导体向内设置的沟道区。源极和漏极区域形成在半导体衬底中，每个设置在沟道区域的一个边缘附近。半导体衬底和源极和漏极区域具有相关联的底壁结电容。使用瞬时增强扩散退火来影响与源区和漏区相关的离子浓度分布，导致源区和漏区的离子浓度分布的增加平衡以及与半导体衬底相关联的离子浓度，这导致减少的底壁结电容。

5. 发明授权

US07038258B2 Semiconductor device having a localized halo implant therein and method of manufacture therefor 有权
标题翻译：具有局部晕轮植入物的半导体器件及其制造方法
公开(公告)号：US07038258B2
公开(公告)日：2006-05-02
申请号：US10913594
申请日：2004-08-05
申请人： Kaiping Liu , Zhiqiang Wu
发明人： Kaiping Liu , Zhiqiang Wu
IPC分类号： H01L27/148 , H01L21/336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L21/823807 , H01L29/66537 , H01L29/78
摘要： The present invention provides a semiconductor device 200 having a localized halo implant 250 located therein, a method of manufacture therefore and an integrated circuit including the semiconductor device. In one embodiment, the semiconductor device 200 includes a gate 244 located over a substrate 210, the substrate 210 having a source and a drain 230 located therein. In the same embodiment, located adjacent each of the source and drain 230 are localized halo implants 250, each of the localized halo implants 250 having a vertical implant region 260 and an angled implant region 265. Further, at an intersection of the vertical implant region 260 and the angled implant region 265 is an area of peak concentration.
摘要翻译：本发明提供一种半导体器件200，其具有位于其中的局部晕轮植入物250，因此制造方法以及包括该半导体器件的集成电路。在一个实施例中，半导体器件200包括位于衬底210上的栅极244，衬底210具有位于其中的源极和漏极230。在相同的实施例中，邻近源极和漏极230中的每一个定位的晕轮植入物250，每个局部晕轮植入物250具有垂直注入区域260和倾斜的注入区域265。此外，在垂直注入区域260和倾斜注入区域265的交点处是峰值浓度的区域。

6. 发明授权

US07029967B2 Silicide method for CMOS integrated circuits 有权
标题翻译： CMOS集成电路的硅化法
公开(公告)号：US07029967B2
公开(公告)日：2006-04-18
申请号：US10896599
申请日：2004-07-21
申请人： Song Zhao , Sue E. Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald S. Miles , Duofeng Yue , Lance S. Robertson
发明人： Song Zhao , Sue E. Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald S. Miles , Duofeng Yue , Lance S. Robertson
IPC分类号： H01L21/8238 , H01L21/331
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/823835 , H01L29/665
摘要： A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.
摘要翻译：描述了在源区和漏区（160,170）中形成金属硅化物区域的方法。在源极和漏极区域（160,170）的热退火之前，将锗注入到与栅极结构（60,70）相邻形成的侧壁结构（90,95）附近的半导体衬底中。植入的锗物质在半导体衬底中的位置将与源区和漏区（160,170）重叠。在源极和漏极区域（160,170）的热退火之后，注入的锗防止形成金属硅化物尖峰。

7. 发明申请

US20060019478A1 Silicide method for CMOS integrated circuits 有权
公开(公告)号：US20060019478A1
公开(公告)日：2006-01-26
申请号：US10896599
申请日：2004-07-21
申请人： Song Zhao , Sue Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald Miles , Duofeng Yue , Lance Robertson
发明人： Song Zhao , Sue Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald Miles , Duofeng Yue , Lance Robertson
IPC分类号： H01L21/28
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/823835 , H01L29/665
摘要： A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.

8. 发明申请

US20050263897A1 Reducing the migration of grain boundaries 有权
公开(公告)号：US20050263897A1
公开(公告)日：2005-12-01
申请号：US11182929
申请日：2005-07-15
申请人： Kaiping Liu , Zhiqiang Wu , Jihong Chen
发明人： Kaiping Liu , Zhiqiang Wu , Jihong Chen
IPC分类号： H01L21/00 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/44 , H01L21/461 , H01L23/48 , H01L23/52 , H01L29/40 , H01L29/49
CPC分类号： H01L21/28035 , H01L29/4916
摘要： A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.

9. 发明申请

US20050012149A1 Semiconductor device having a localized halo implant therein and method of manufacture therefor 有权
标题翻译：具有局部晕轮植入物的半导体器件及其制造方法
公开(公告)号：US20050012149A1
公开(公告)日：2005-01-20
申请号：US10913594
申请日：2004-08-05
申请人： Kaiping Liu , Zhiqiang Wu
发明人： Kaiping Liu , Zhiqiang Wu
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/78 , H01L29/76 , H01L31/062
CPC分类号： H01L29/66492 , H01L21/26586 , H01L21/823807 , H01L29/66537 , H01L29/78
摘要： The present invention provides a semiconductor device 200 having a localized halo implant 250 located therein, a method of manufacture therefore and an integrated circuit including the semiconductor device. In one embodiment, the semiconductor device 200 includes a gate 244 located over a substrate 210, the substrate 210 having a source and a drain 230 located therein. In the same embodiment, located adjacent each of the source and drain 230 are localized halo implants 250, each of the localized halo implants 250 having a vertical implant region 260 and an angled implant region 265. Further, at an intersection of the vertical implant region 260 and the angled implant region 265 is an area of peak concentration.
摘要翻译：本发明提供一种半导体器件200，其具有位于其中的局部晕轮植入物250，因此制造方法以及包括该半导体器件的集成电路。在一个实施例中，半导体器件200包括位于衬底210上的栅极244，衬底210具有位于其中的源极和漏极230。在相同的实施例中，位于源极和漏极230的每一个附近的是局部晕轮注入250，每个局部晕轮植入物250具有垂直注入区域260和倾斜注入区域265.此外，在垂直注入区域 260和角度注入区域265是峰值浓度的区域。

10. 发明申请

US20140001526A1 Analog Floating-Gate Capacitor with Improved Data Retention in a Silicided Integrated Circuit 有权
标题翻译：在硅化集成电路中具有改进的数据保持性的模拟浮栅电容器
公开(公告)号：US20140001526A1
公开(公告)日：2014-01-02
申请号：US13534865
申请日：2012-06-27
申请人： Kaiping Liu , Amitava Chatterjee , Imran Mahmood Khan
发明人： Kaiping Liu , Amitava Chatterjee , Imran Mahmood Khan
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L29/66181 , H01L27/0629 , H01L27/0805 , H01L27/11558 , H01L28/60
摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.
摘要翻译：集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。模拟浮栅电极形成为多晶硅栅极电平，并且包括用作晶体管栅电极的部分，金属对多晶硅存储电容器的板以及多至多晶硅隧道电容器的板。由氮化硅顶层下面的二氧化硅层构成的硅化物阻挡膜阻止在电极上形成硅化物包层，而诸如多晶硅对金属电容器的集成电路中的其它多晶硅结构是硅化物 - 包裹在硅化之后，在剩余的多晶硅结构上沉积电容器电介质，随后形成上部金属板。

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