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1. 发明授权

US07231626B2 Method of implementing an engineering change order in an integrated circuit design by windows 有权
标题翻译：通过Windows实现集成电路设计中的工程变更顺序的方法
公开(公告)号：US07231626B2
公开(公告)日：2007-06-12
申请号：US11015123
申请日：2004-12-17
申请人： Jason K. Hoff , Viswanathan Lakshmanan , Michael Josephides , Daniel W. Prevedel , Richard D. Blinne , Johathan P. Kuppinger
发明人： Jason K. Hoff , Viswanathan Lakshmanan , Michael Josephides , Daniel W. Prevedel , Richard D. Blinne , Johathan P. Kuppinger
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/04
摘要： A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.
摘要翻译：一种实现工程变更订单的方法包括以下步骤：（a）作为输入接收集成电路设计; （b）作为输入接收集成电路设计的工程变更订单; （c）在集成电路设计中创建至少一个窗口，其包围由工程改变顺序引入的集成电路设计的变化，其中窗口由限定小于集成电路的整个区域的区域的坐标界定设计; （d）执行集成电路设计的路由，该路由排除不包括窗口的任何网络的路由; （e）将由窗口坐标限定的集成电路设计的副本中的区域替换为增量路由的结果以生成修订的集成电路设计; 和（f）产生经修订的集成电路设计的输出。

2. 发明授权

US07302654B2 Method of automating place and route corrections for an integrated circuit design from physical design validation 有权
标题翻译：通过物理设计验证自动化集成电路设计的位置和路线校正方法
公开(公告)号：US07302654B2
公开(公告)日：2007-11-27
申请号：US10977386
申请日：2004-10-29
申请人： Viswanathan Lakshmanan , Michael Josephides , Richard D. Blinne
发明人： Viswanathan Lakshmanan , Michael Josephides , Richard D. Blinne
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the physical design validation; (c) identifying locations in the integrated circuit design from the results database for making design corrections according to a post-processing rule deck so that the locations of the design corrections comply with the set of design rules; and (d) implementing the design corrections in the integrated circuit design.
摘要翻译：一种用于自动校正集成电路设计中的错误的方法和计算机程序产品包括以下步骤：（a）执行集成电路设计的物理设计验证以验证是否符合一组设计规则; （b）生成通过物理设计验证检测到的设计规则违规的结果数据库; （c）从结果数据库中识别集成电路设计中的位置，以便根据后处理规则表进行设计更正，使设计更正的位置符合设计规则集; 和（d）在集成电路设计中实现设计校正。

3. 发明授权

US07107559B2 Method of partitioning an integrated circuit design for physical design verification 有权
标题翻译：分离用于物理设计验证的集成电路设计的方法
公开(公告)号：US07107559B2
公开(公告)日：2006-09-12
申请号：US10697357
申请日：2003-10-29
申请人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
发明人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： A method of partitioning an integrated circuit design for physical design verification includes steps of receiving as input a representation of an integrated circuit design having a number of physical design layers and a composite run deck specifying rule checks to be performed on the integrated circuit design. The composite run deck is partitioned into partitioned run decks so that the number of physical design layers referenced by each of the partitioned run decks is a minimum. The representation of the integrated circuit design is parsed to filter only the physical design layers required for each of the partitioned run decks into a filtered data deck for each of the partitioned run decks. The filtered data deck is generated as output for each of the partitioned run decks.
摘要翻译：对用于物理设计验证的集成电路设计进行分区的方法包括以下步骤：接收作为输入的具有多个物理设计层的集成电路设计的表示，以及指定要对集成电路设计执行的规则检查的复合运行层。复合运行甲板被划分为分区运行甲板，使得每个分区运行甲板引用的物理设计层的数量是最小的。解析集成电路设计的表示仅将每个分区运行平台所需的物理设计层过滤到每个分区运行卡的过滤数据卡。过滤的数据记录卡是为每个分区运行记录卡的输出生成的。

4. 发明授权

US07853901B2 Unified layer stack architecture 有权
标题翻译：统一层堆栈架构
公开(公告)号：US07853901B2
公开(公告)日：2010-12-14
申请号：US12109501
申请日：2008-04-25
申请人： Viswanathan Lakshmanan , Thomas R. O'Brien , Richard D. Blinne
发明人： Viswanathan Lakshmanan , Thomas R. O'Brien , Richard D. Blinne
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.
摘要翻译：一种用于生产数字集成电路设计系列的方法，其中家族具有最高级别的设计和至少一个较低级别的设计。最高水平的设计是首次生产。然后，在没有用户干预的编程计算系统中，自动处理最高级别的设计以选择性地移除至少一个预定的金属层。至少一个去除的金属层的最近的剩余覆盖层被自动映射到至少一个移除的金属层的最接近的剩余的下层，由此产生至少一个较低级设计。

5. 发明申请

US20090271755A1 Unified Layer Stack Architecture 有权
标题翻译：统一层堆栈架构
公开(公告)号：US20090271755A1
公开(公告)日：2009-10-29
申请号：US12109501
申请日：2008-04-25
申请人： Viswanathan Lakshmanan , Thomas R. O'Brien , Richard D. Blinne
发明人： Viswanathan Lakshmanan , Thomas R. O'Brien , Richard D. Blinne
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.
摘要翻译：一种用于生产数字集成电路设计系列的方法，其中家族具有最高级别的设计和至少一个较低级别的设计。最高水平的设计是首次生产。然后，在没有用户干预的编程计算系统中，自动处理最高级别的设计以选择性地移除至少一个预定的金属层。至少一个去除的金属层的最近的剩余覆盖层被自动映射到至少一个移除的金属层的最接近的剩余的下层，由此产生至少一个较低级设计。

6. 发明授权

US07219317B2 Method and computer program for verifying an incremental change to an integrated circuit design 有权
标题翻译：用于验证集成电路设计的增量变化的方法和计算机程序
公开(公告)号：US07219317B2
公开(公告)日：2007-05-15
申请号：US10828408
申请日：2004-04-19
申请人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
发明人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A method and computer program product for verifying an incremental change to an integrated circuit design include receiving as input an integrated circuit design database and an engineering change order. Objects in the integrated circuit design database are identified and marked to indicate a current state of the integrated circuit design database. The engineering change order is applied to the integrated circuit design database, and the integrated circuit design database is analyzed to generate a list of incremental changes to the integrated circuit design database resulting from the engineering change order. Objects in the integrated circuit design database included in the list of incremental changes are identified and marked to distinguish objects in the integrated circuit design database that were changed from the current state. The marked integrated circuit design database distinguishing the objects that were changed from the current state is generated as output.
摘要翻译：用于验证集成电路设计的增量变化的方法和计算机程序产品包括接收集成电路设计数据库和工程变更顺序作为输入。集成电路设计数据库中的对象被识别并标记为指示集成电路设计数据库的当前状态。工程变更单适用于集成电路设计数据库，并对集成电路设计数据库进行分析，以生成由工程变更订单产生的集成电路设计数据库的增量变化清单。集成电路设计数据库中包含增量变化列表中的对象被识别并标记为区分集成电路设计数据库中与当前状态相对应的对象。标记的集成电路设计数据库将区分从当前状态改变的对象作为输出生成。

7. 发明申请

US20060136855A1 Method of implementing an engineering change order in an integrated circuit design by windows 有权
标题翻译：通过Windows实现集成电路设计中的工程变更顺序的方法
公开(公告)号：US20060136855A1
公开(公告)日：2006-06-22
申请号：US11015123
申请日：2004-12-17
申请人： Jason Hoff , Viswanathan Lakshmanan , Michael Josephides , Daniel Prevedel , Richard Blinne , Jonathan Kuppinger
发明人： Jason Hoff , Viswanathan Lakshmanan , Michael Josephides , Daniel Prevedel , Richard Blinne , Jonathan Kuppinger
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/04
摘要： A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.
摘要翻译：一种实现工程变更订单的方法包括以下步骤：（a）接收作为输入的集成电路设计; （b）作为输入接收集成电路设计的工程变更订单; （c）在集成电路设计中创建至少一个窗口，其包围由工程改变顺序引入的集成电路设计的变化，其中窗口由限定小于集成电路的整个区域的区域的坐标界定设计; （d）执行集成电路设计的路由，该路由排除不包括窗口的任何网络的路由; （e）将由窗口坐标限定的集成电路设计的副本中的区域替换为增量路由的结果以生成修订的集成电路设计; 和（f）产生经修订的集成电路设计的输出。

8. 发明授权

US08046726B2 Waiver mechanism for physical verification of system designs 失效
标题翻译：系统设计物理验证豁免机制
公开(公告)号：US08046726B2
公开(公告)日：2011-10-25
申请号：US12211238
申请日：2008-09-16
申请人： Viswanathan Lakshmanan , Michael Josephides , Lisa M. Miller
发明人： Viswanathan Lakshmanan , Michael Josephides , Lisa M. Miller
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081
摘要： A method of waiving verification failures is disclosed. The method generally includes the steps of (A) generating a plurality of circuit error files by performing a plurality of physical verifications on a plurality of circuit designs, the circuit error files containing a plurality of circuit errors of the circuit designs, (B) generating a system error file by performing an additional physical verification on a system design, the system error file containing a plurality of system errors of the system design, the system design incorporating the circuit designs and (C) generating a valid error file by removing the circuit errors from the system error file, the valid error file containing a plurality of valid errors comprising a subset of the system errors.
摘要翻译：公开了一种放弃验证失败的方法。该方法通常包括以下步骤：（A）通过在多个电路设计上执行多个物理验证来产生多个电路错误文件，所述电路错误文件包含电路设计的多个电路错误，（B）产生系统错误文件通过在系统设计上执行附加物理验证，系统错误文件包含系统设计的多个系统错误，包含电路设计的系统设计，以及（C）通过去除电路来生成有效的错误文件来自系统错误文件的错误，有效的错误文件包含多个有效的错误，包括系统错误的子集。

9. 发明授权

US06775811B2 Chip design method for designing integrated circuit chips with embedded memories 失效
标题翻译：具有嵌入式存储器的集成电路芯片的芯片设计方法
公开(公告)号：US06775811B2
公开(公告)日：2004-08-10
申请号：US10151826
申请日：2002-05-22
申请人： Viswanathan Lakshmanan , Michael Josephides , Tom R. O'Brien , David A. Morgan
发明人： Viswanathan Lakshmanan , Michael Josephides , Tom R. O'Brien , David A. Morgan
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method of circuit design for designing integrated circuits with one or more embedded memories. A placement is generated for timing critical logic associated with each included embedded memory in a logic design. An augmented memory boundary is generated for said each included memory. Each augmented memory boundary encompasses one embedded memory and associated said timing critical logic.
摘要翻译：一种用于设计具有一个或多个嵌入存储器的集成电路的电路设计方法。在逻辑设计中生成与每个包含的嵌入式存储器相关联的定时关键逻辑的布局。为所述每个包括的存储器生成增强的存储器边界。每个增强的存储器边界包括一个嵌入式存储器和相关联的所述定时关键逻辑。

10. 发明申请

US20100070936A1 WAIVER MECHANISM FOR PHYSICAL VERIFICATION OF SYSTEM DESIGNS 失效
标题翻译：系统设计物理验证的豁免机制
公开(公告)号：US20100070936A1
公开(公告)日：2010-03-18
申请号：US12211238
申请日：2008-09-16
申请人： Viswanathan Lakshmanan , Michael Josephides , Lisa M. Miller
发明人： Viswanathan Lakshmanan , Michael Josephides , Lisa M. Miller
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of waiving verification failures is disclosed. The method generally includes the steps of (A) generating a plurality of circuit error files by performing a plurality of physical verifications on a plurality of circuit designs, the circuit error files containing a plurality of circuit errors of the circuit designs, (B) generating a system error file by performing an additional physical verification on a system design, the system error file containing a plurality of system errors of the system design, the system design incorporating the circuit designs, (C) generating a valid error file by removing the circuit errors from the system error file, the valid error file containing a plurality of valid errors comprising a subset of the system errors and (D) storing the valid error file in a recording medium.
摘要翻译：公开了一种放弃验证失败的方法。该方法通常包括以下步骤：（A）通过在多个电路设计上执行多个物理验证来产生多个电路错误文件，所述电路错误文件包含电路设计的多个电路错误，（B）产生系统错误文件，通过对系统设计进行附加物理验证，系统错误文件包含系统设计的多个系统错误，包含电路设计的系统设计，（C）通过去除电路来生成有效的错误文件来自系统错误文件的错误，包含多个有效错误的有效错误文件，包括系统错误的子集，以及（D）将有效的错误文件存储在记录介质中。

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