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1. 发明授权

US07389388B2 Data processing system and method for efficient communication utilizing an in coherency state 有权
标题翻译：用于在一致性状态下有效通信的数据处理系统和方法
公开(公告)号：US07389388B2
公开(公告)日：2008-06-17
申请号：US11055305
申请日：2005-02-10
申请人： Jason F. Cantin , James S. Fields, Jr. , Steven R. Kunkel , William J. Starke
发明人： Jason F. Cantin , James S. Fields, Jr. , Steven R. Kunkel , William J. Starke
IPC分类号： G06F13/00
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。第一相关域包括第一高速缓冲存储器，并且第二相干域包括相干第二高速缓冲存储器。数据处理系统的第一相干域内的第一高速缓冲存储器在与地址标签和一致性状态字段相关联的存储位置中保存存储器块。相关性状态字段被设置为指示地址标签有效的状态，存储位置不包含有效数据，并且该存储器块可能仅在第一相干域内被缓存。

2. 发明授权

US07747826B2 Data processing system and method for efficient communication utilizing an in coherency state 有权
标题翻译：用于在一致性状态下有效通信的数据处理系统和方法
公开(公告)号：US07747826B2
公开(公告)日：2010-06-29
申请号：US12103564
申请日：2008-04-15
申请人： Jason F. Cantin , James S. Fields, Jr. , Steven R. Kunkel , William J. Starke
发明人： Jason F. Cantin , James S. Fields, Jr. , Steven R. Kunkel , William J. Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。第一相关域包括第一高速缓冲存储器，并且第二相干域包括相干第二高速缓冲存储器。数据处理系统的第一相干域内的第一高速缓冲存储器在与地址标签和一致性状态字段相关联的存储位置中保存存储器块。相关性状态字段被设置为指示地址标签有效的状态，存储位置不包含有效数据，并且该存储器块可能仅在第一相干域内被缓存。

3. 发明申请

US20080215821A1 DATA PROCESSING SYSTEM AND METHOD FOR EFFICIENT COMMUNICATION UTILIZING AN IN COHERENCY STATE 有权
标题翻译：数据处理系统和方法，用于高效率通信
公开(公告)号：US20080215821A1
公开(公告)日：2008-09-04
申请号：US12103564
申请日：2008-04-15
申请人： Jason F. Cantin , James S. Fields , Steven R. Kunkel , William J. Starke
发明人： Jason F. Cantin , James S. Fields , Steven R. Kunkel , William J. Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。第一相关域包括第一高速缓冲存储器，并且第二相干域包括相干第二高速缓冲存储器。数据处理系统的第一相干域内的第一高速缓冲存储器在与地址标签和一致性状态字段相关联的存储位置中保存存储器块。相关性状态字段被设置为指示地址标签有效的状态，存储位置不包含有效数据，并且该存储器块可能仅在第一相干域内被缓存。

4. 发明申请

US20110302374A1 LOCAL AND GLOBAL MEMORY REQUEST PREDICTOR 有权
标题翻译：本地和全球内存请求预测者
公开(公告)号：US20110302374A1
公开(公告)日：2011-12-08
申请号：US12793795
申请日：2010-06-04
申请人： Jason F. Cantin , Steven R. Kunkel
发明人： Jason F. Cantin , Steven R. Kunkel
IPC分类号： G06F12/08
CPC分类号： G06F12/0813
摘要： A method, circuit arrangement, and design structure utilize broadcast prediction data to determine whether to globally broadcast a memory request in a computing system of the type that includes a plurality of nodes, each node including a plurality of processing units. The method includes updating broadcast prediction data for a cache line associated with a first memory request within a hardware-based broadcast prediction data structure in turn associated with a first processing unit in response to the first memory request, the broadcast prediction data for the cache line including data associated with a history of ownership of the cache line. The method further comprises accessing the broadcast prediction data structure and determining whether to perform an early broadcast of a second memory request to a second node based on broadcast prediction data within the broadcast prediction data structure in response to that second memory request associated with the cache line.
摘要翻译：一种方法，电路装置和设计结构利用广播预测数据来确定是否在包括多个节点的类型的计算系统中全局广播存储器请求，每个节点包括多个处理单元。所述方法包括响应于第一存储器请求，在基于硬件的广播预测数据结构中更新与第一存储器请求相关联的高速缓存行的广播预测数据，该第一存储器请求与第一处理单元相对应，用于高速缓存行的广播预测数据包括与高速缓存行的所有权历史相关联的数据。该方法还包括响应于与高速缓存行相关联的第二存储器请求，基于广播预测数据结构内的广播预测数据，来访问广播预测数据结构并确定是否对第二节点执行第二存储器请求的早期广播。

5. 发明授权

US08397030B2 Efficient region coherence protocol for clustered shared-memory multiprocessor systems 有权
标题翻译：用于集群共享内存多处理器系统的高效区域一致性协议
公开(公告)号：US08397030B2
公开(公告)日：2013-03-12
申请号：US12144759
申请日：2008-06-24
申请人： Jason F. Cantin , Steven R. Kunkel
发明人： Jason F. Cantin , Steven R. Kunkel
IPC分类号： G06F12/08
CPC分类号： G06F12/0833 , G06F12/0822
摘要： A system and method of a region coherence protocol for use in Region Coherence Arrays (RCAs) deployed in clustered shared-memory multiprocessor systems which optimize cache-to-cache transfers by allowing broadcast memory requests to be provided to only a portion of a clustered shared-memory multiprocessor system. Interconnect hierarchy levels can be devised for logical groups of processors, processors on the same chip, processors on chips aggregated into a multichip module, multichip modules on the same printed circuit board, and for processors on other printed circuit boards or in other cabinets. The present region coherence protocol includes, for example, one bit per level of interconnect hierarchy, such that the one bit has a value of “1” to indicate that there may be processors caching copies of lines from the region at that level of the interconnect hierarchy, and the one bit has a value of “0” to indicate that there are no cached copies of any lines from the region at that respective level of the interconnect hierarchy.
摘要翻译：区域一致性协议的系统和方法，用于部署在群集共享存储器多处理器系统中的区域相干阵列（RCA），其通过允许广播存储器请求仅提供给集群共享的一部分来优化高速缓存到高速缓存传输内存多处理器系统。可以为逻辑组处理器，同一芯片上的处理器，集成到多芯片模块中的芯片上的处理器，同一印刷电路板上的多芯片模块以及其他印刷电路板或其他机柜中的处理器设计互连层级。当前区域相干协议包括例如每层次的互连层级中的一位，使得一位具有值1以指示可以存在处理器从互连层级的该级别的区域缓存行的副本，并且一位的值为0，表示在互连层次结构的相应级别的区域中没有任何行的缓存副本。

6. 发明申请

US20100281221A1 Shared Data Prefetching with Memory Region Cache Line Monitoring 有权
标题翻译：使用内存区域缓存线路监控进行共享数据预取
公开(公告)号：US20100281221A1
公开(公告)日：2010-11-04
申请号：US12432823
申请日：2009-04-30
申请人： Jason F. Cantin , Steven R. Kunkel
发明人： Jason F. Cantin , Steven R. Kunkel
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0813 , G06F12/0815 , G06F2212/6022
摘要： A method, circuit arrangement, and design structure for prefetching data for responding to a memory request, in a shared memory computing system of the type that includes a plurality of nodes, is provided. Prefetching data comprises, receiving, in response to a first memory request by a first node, presence data for a memory region associated with the first memory request from a second node that sources data requested by the first memory request, and selectively prefetching at least one cache line from the memory region based on the received presence data. Responding to a memory request comprises tracking presence data associated with memory regions associated with cached cache lines in the first node, and, in response to a memory request by a second node, forwarding the tracked presence data for a memory region associated with the memory request to the second node.
摘要翻译：提供了在包括多个节点的类型的共享存储器计算系统中的用于预取数据以响应存储器请求的方法，电路布置和设计结构。预取数据包括：响应于第一节点的第一存储器请求，接收来自第二节点的与第一存储器请求相关联的存储器区域的存在数据，该第二节点发送由第一存储器请求请求的数据，并且选择性地预取至少一个基于接收的存在数据从存储器区域的高速缓存行。响应于存储器请求包括跟踪与第一节点中与高速缓存行相关联的存储器区域的存在数据，并且响应于第二节点的存储器请求，转发与存储器请求相关联的存储器区域的跟踪存在数据到第二个节点。

7. 发明申请

US20100281220A1 Predictive ownership control of shared memory computing system data 有权
标题翻译：共享内存计算系统数据的预测所有权控制
公开(公告)号：US20100281220A1
公开(公告)日：2010-11-04
申请号：US12432835
申请日：2009-04-30
申请人： Jason F. Cantin , Steven R. Kunkel
发明人： Jason F. Cantin , Steven R. Kunkel
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/084 , G06F9/528 , G06F12/0842 , G06F12/126 , G06F2212/1016
摘要： A method, circuit arrangement, and design structure utilize a lock prediction data structure to control ownership of a cache line in a shared memory computing system. In a first node among the plurality of nodes, lock prediction data in a hardware-based lock prediction data structure for a cache line associated with a first memory request is updated in response to that first memory request, wherein at least a portion of the lock prediction data is predictive of whether the cache line is associated with a release operation. The lock prediction data is then accessed in response to a second memory request associated with the cache line and issued by a second node and a determination is made as to whether to transfer ownership of the cache line from the first node to the second node based at least in part on the accessed lock prediction data.
摘要翻译：方法，电路布置和设计结构利用锁预测数据结构来控制共享存储器计算系统中的高速缓存行的所有权。在所述多个节点中的第一节点中，响应于所述第一存储器请求来更新与用于与第一存储器请求相关联的高速缓存行的基于硬件的锁预测数据结构中的预测数据锁定，其中所述锁的至少一部分预测数据预测高速缓存行是否与释放操作相关联。然后，锁定预测数据被响应于与高速缓存线相关联并由第二节点发出的第二存储器请求而被访问，并且基于在第二节点处是否将高速缓存行的所有权从第一节点转移到第二节点进行确定至少部分地基于所访问的锁定预测数据。

8. 发明申请

US20090319726A1 Efficient Region Coherence Protocol for Clustered Shared-Memory Multiprocessor Systems 有权
标题翻译：用于集群共享内存多处理器系统的高效区域一致性协议
公开(公告)号：US20090319726A1
公开(公告)日：2009-12-24
申请号：US12144759
申请日：2008-06-24
申请人： Jason F. Cantin , Steven R. Kunkel
发明人： Jason F. Cantin , Steven R. Kunkel
IPC分类号： G06F12/08
CPC分类号： G06F12/0833 , G06F12/0822
摘要： A system and method of a region coherence protocol for use in Region Coherence Arrays (RCAs) deployed in clustered shared-memory multiprocessor systems which optimize cache-to-cache transfers by allowing broadcast memory requests to be provided to only a portion of a clustered shared-memory multiprocessor system. Interconnect hierarchy levels can be devised for logical groups of processors, processors on the same chip, processors on chips aggregated into a multichip module, multichip modules on the same printed circuit board, and for processors on other printed circuit boards or in other cabinets. The present region coherence protocol includes, for example, one bit per level of interconnect hierarchy, such that the one bit has a value of “1” to indicate that there may be processors caching copies of lines from the region at that level of the interconnect hierarchy, and the one bit has a value of “0” to indicate that there are no cached copies of any lines from the region at that respective level of the interconnect hierarchy.
摘要翻译：区域一致性协议的系统和方法，用于部署在群集共享存储器多处理器系统中的区域相干阵列（RCA），其通过允许广播存储器请求仅提供给集群共享的一部分来优化高速缓存到高速缓存传输内存多处理器系统。可以为逻辑组处理器，同一芯片上的处理器，集成到多芯片模块中的芯片上的处理器，同一印刷电路板上的多芯片模块以及其他印刷电路板或其他机柜中的处理器设计互连层级。当前的区域相干协议例如包括每级互连层级的一位，使得一位具有值“1”，以指示可能存在处理器从互连级别的区域的区域缓存行的副本层次结构，并且一位具有值“0”，表示在互连层次结构的相应级别的区域中没有任何行的缓存副本。

9. 发明授权

US08370584B2 Predictive ownership control of shared memory computing system data 有权
标题翻译：共享内存计算系统数据的预测所有权控制
公开(公告)号：US08370584B2
公开(公告)日：2013-02-05
申请号：US13530857
申请日：2012-06-22
申请人： Jason F. Cantin , Steven R. Kunkel
发明人： Jason F. Cantin , Steven R. Kunkel
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F9/528 , G06F12/0842 , G06F12/126 , G06F2212/1016
摘要： A method, circuit arrangement, and design structure utilize a lock prediction data structure to control ownership of a cache line in a shared memory computing system. In a first node among the plurality of nodes, lock prediction data in a hardware-based lock prediction data structure for a cache line associated with a first memory request is updated in response to that first memory request, wherein at least a portion of the lock prediction data is predictive of whether the cache line is associated with a release operation. The lock prediction data is then accessed in response to a second memory request associated with the cache line and issued by a second node and a determination is made as to whether to transfer ownership of the cache line from the first node to the second node based at least in part on the accessed lock prediction data.
摘要翻译：方法，电路布置和设计结构利用锁预测数据结构来控制共享存储器计算系统中的高速缓存行的所有权。在所述多个节点中的第一节点中，响应于所述第一存储器请求来更新与用于与第一存储器请求相关联的高速缓存行的基于硬件的锁预测数据结构中的预测数据锁定，其中所述锁的至少一部分预测数据预测高速缓存行是否与释放操作相关联。然后，锁定预测数据被响应于与高速缓存线相关联并由第二节点发出的第二存储器请求而被访问，并且基于在第二节点处是否将高速缓存行的所有权从第一节点转移到第二节点进行确定至少部分地基于所访问的锁定预测数据。

10. 发明申请

US20120265942A1 PREDICTIVE OWNERSHIP CONTROL OF SHARED MEMORY COMPUTING SYSTEM DATA 有权
标题翻译：共享内存计算系统数据的预测所有权控制
公开(公告)号：US20120265942A1
公开(公告)日：2012-10-18
申请号：US13530857
申请日：2012-06-22
申请人： Jason F. Cantin , Steven R. Kunkel
发明人： Jason F. Cantin , Steven R. Kunkel
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F9/528 , G06F12/0842 , G06F12/126 , G06F2212/1016
摘要： A method, circuit arrangement, and design structure utilize a lock prediction data structure to control ownership of a cache line in a shared memory computing system. In a first node among the plurality of nodes, lock prediction data in a hardware-based lock prediction data structure for a cache line associated with a first memory request is updated in response to that first memory request, wherein at least a portion of the lock prediction data is predictive of whether the cache line is associated with a release operation. The lock prediction data is then accessed in response to a second memory request associated with the cache line and issued by a second node and a determination is made as to whether to transfer ownership of the cache line from the first node to the second node based at least in part on the accessed lock prediction data.
摘要翻译：方法，电路布置和设计结构利用锁预测数据结构来控制共享存储器计算系统中的高速缓存行的所有权。在所述多个节点中的第一节点中，响应于所述第一存储器请求来更新与用于与第一存储器请求相关联的高速缓存行的基于硬件的锁预测数据结构中的预测数据锁定，其中所述锁的至少一部分预测数据预测高速缓存行是否与释放操作相关联。然后，锁定预测数据被响应于与高速缓存线相关联并由第二节点发出的第二存储器请求而被访问，并且基于在第二节点处是否将高速缓存行的所有权从第一节点转移到第二节点进行确定至少部分地基于所访问的锁定预测数据。

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