专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09201444B2 Clock generation for timing communications with ranks of memory devices 有权
标题翻译：用于与存储器设备等级进行定时通信的时钟生成
公开(公告)号：US09201444B2
公开(公告)日：2015-12-01
申请号：US13990370
申请日：2011-11-09
申请人： Jared L. Zerbe , Ian P. Shaeffer , John Eble
发明人： Jared L. Zerbe , Ian P. Shaeffer , John Eble
IPC分类号： G06F1/04 , G06F1/12 , G06F13/16 , G06F1/10 , G11C7/22 , G06F1/06 , G06F1/08 , H04L7/033 , G11C7/04
CPC分类号： G06F13/1689 , G06F1/04 , G06F1/06 , G06F1/08 , G06F1/10 , G06F13/161 , G06F13/1657 , G11C7/04 , G11C7/222 , H04L7/033
摘要： A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
摘要翻译：存储器控制器包括时钟发生器，用于产生第一时钟信号和定时电路，以从第一时钟信号产生第二时钟信号。第二时钟信号与相应等级中的多个存储器件中的任何一个存储器件进行通信，包括第一等级中的第一存储器件和第二等级的第二存储器件。定时电路被配置为基于与第二存储器设备相关联的校准数据和与来自至少第一存储器的反馈相关联的定时调整数据来调整存储器控制器与第二存储器件通信时的第一时钟信号的相位设备。

2. 发明申请

US20130254585A1 CLOCK GENERATION FOR TIMING COMMUNICATIONS WITH RANKS OF MEMORY DEVICES 有权
标题翻译：用于与存储器件排序进行定时通信的时钟生成器
公开(公告)号：US20130254585A1
公开(公告)日：2013-09-26
申请号：US13990370
申请日：2011-11-09
申请人： Jared L. Zerbe , Ian P. Shaeffer , John Eble
发明人： Jared L. Zerbe , Ian P. Shaeffer , John Eble
IPC分类号： G06F1/04
CPC分类号： G06F13/1689 , G06F1/04 , G06F1/06 , G06F1/08 , G06F1/10 , G06F13/161 , G06F13/1657 , G11C7/04 , G11C7/222 , H04L7/033
摘要： A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
摘要翻译：存储器控制器包括时钟发生器，用于产生第一时钟信号和定时电路，以从第一时钟信号产生第二时钟信号。第二时钟信号与相应等级中的多个存储器件中的任何一个存储器件进行通信，包括第一等级中的第一存储器件和第二等级的第二存储器件。定时电路被配置为基于与第二存储器设备相关联的校准数据和与来自至少第一存储器的反馈相关联的定时调整数据来调整存储器控制器与第二存储器件通信时的第一时钟信号的相位设备。

3. 发明申请

US20130148447A1 Reducing Power Consumption in a Memory System 审中-公开
标题翻译：降低存储系统中的功耗
公开(公告)号：US20130148447A1
公开(公告)日：2013-06-13
申请号：US13707540
申请日：2012-12-06
申请人： Ian P. Shaeffer , Jared L. Zerbe , Frederick A. Ware
发明人： Ian P. Shaeffer , Jared L. Zerbe , Frederick A. Ware
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C5/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C7/225 , G11C29/24 , G11C2207/2227
摘要： Components of a memory system, such as a memory controller or memory device, that operate in different power states to reduce the overall power consumption of the memory system. In some of the power states, distribution circuitry that distributes a timing signal within the components may be powered on when the output of the distribution circuitry is needed. In other power states, the distribution circuitry may be powered off when the output of the distribution circuitry is not needed. Additionally, power states in the memory device may be triggered off memory access commands issued by the memory controller.
摘要翻译：存储器系统的组件，例如存储器控制器或存储器件，它们以不同的功率状态工作，以减少存储器系统的总功耗。在一些功率状态中，当需要分配电路的输出时，可以在组件内分配定时信号的分配电路被通电。在其他电源状态下，当不需要分配电路的输出时，分配电路可能会关闭电源。此外，存储器设备中的电源状态可能被存储器控制器发出的存储器访问命令触发。

4. 发明授权

US08610459B2 Controlling on-die termination in a dynamic random access memory device 有权
标题翻译：控制动态随机存取存储器件中的管芯端接
公开(公告)号：US08610459B2
公开(公告)日：2013-12-17
申请号：US13480298
申请日：2012-05-24
申请人： Kyung Suk Oh , Ian P. Shaeffer
发明人： Kyung Suk Oh , Ian P. Shaeffer
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , G06F3/0605 , G06F3/0659 , G06F3/0685 , G06F13/4086 , G11C11/401 , G11C11/4063 , G11C11/4093 , G11C11/41 , G11C11/413 , G11C11/417 , G11C11/419 , G11C16/06 , G11C16/26 , G11C16/32 , H03K19/017545
摘要： An integrated circuit device transmits, to a dynamic random access memory device (DRAM), a write command indicating that write data is to be sampled by a data interface of the DRAM, and a plurality of commands that specify programming a plurality of control values into a plurality of corresponding registers in the DRAM. The plurality of control values include first and second control values that indicate respective first and second terminations that the DRAM is to apply to the data interface during a time interval that begins a predetermined amount of time after the DRAM receives the write command, the first termination to be applied during a first portion of the time interval while the data interface is sampling the write data and the second termination to be applied during a second portion of the time interval after the write data is sampled.
摘要翻译：集成电路装置向动态随机存取存储装置（DRAM）发送指示写入数据由DRAM的数据接口采样的写入命令，以及指定多个控制值的编程的多个命令 DRAM中的多个对应的寄存器。多个控制值包括第一和第二控制值，其指示在DRAM接收到写命令之后开始预定时间量的时间间隔期间DRAM应用于数据接口的相应的第一和第二终端，第一终端在时间间隔的第一部分期间被应用，同时数据接口对在写入数据进行采样之后的时间间隔的第二部分期间对写入数据和第二终止进行采样。

5. 发明授权

US08339878B2 Integrated circuit with staggered signal output 有权
标题翻译：具有交错信号输出的集成电路
公开(公告)号：US08339878B2
公开(公告)日：2012-12-25
申请号：US13336851
申请日：2011-12-23
申请人： Ian P. Shaeffer , Bret Stott , Benedict C. Lau
发明人： Ian P. Shaeffer , Bret Stott , Benedict C. Lau
IPC分类号： G11C7/00
CPC分类号： G11C7/1063 , G06F12/00 , G06F13/1689 , G11C7/1072
摘要： A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
摘要翻译：具有时间交错请求信号输出的存储器控制器。产生第一定时信号，同时产生具有相对于第一定时信号的第一相位差的第二定时信号。响应于第一定时信号发送地址值，响应于构成第一存储器访问请求的第二定时信号，地址值和控制值发送控制值。

6. 发明申请

US20120188835A1 INTEGRATED CIRCUIT WITH STAGGERED SIGNAL OUTPUT 有权
标题翻译：集成电路与STAGGERED信号输出
公开(公告)号：US20120188835A1
公开(公告)日：2012-07-26
申请号：US13336851
申请日：2011-12-23
申请人： Ian P. Shaeffer , Bret Stott , Benedict C. Lau
发明人： Ian P. Shaeffer , Bret Stott , Benedict C. Lau
IPC分类号： G11C8/08 , G11C8/18 , G11C7/00
CPC分类号： G11C7/1063 , G06F12/00 , G06F13/1689 , G11C7/1072
摘要： A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
摘要翻译：具有时间交错请求信号输出的存储器控制器。产生第一定时信号，同时产生具有相对于第一定时信号的第一相位差的第二定时信号。响应于第一定时信号发送地址值，响应于构成第一存储器访问请求的第二定时信号，地址值和控制值发送控制值。

7. 发明授权

US08188762B2 Controlling dynamic selection of on-die termination 有权
标题翻译：控制片上端接的动态选择
公开(公告)号：US08188762B2
公开(公告)日：2012-05-29
申请号：US13180550
申请日：2011-07-12
申请人： Kyung Suk Oh , Ian P. Shaeffer
发明人： Kyung Suk Oh , Ian P. Shaeffer
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , G06F3/0605 , G06F3/0659 , G06F3/0685 , G06F13/4086 , G11C11/401 , G11C11/4063 , G11C11/4093 , G11C11/41 , G11C11/413 , G11C11/417 , G11C11/419 , G11C16/06 , G11C16/26 , G11C16/32 , H03K19/017545
摘要： A control component outputs to an integrated circuit device an indication to apply one of a plurality of controllable termination impedance configurations at a data input of the integrated circuit device. The indication causes the integrated circuit device to apply a first of the controllable termination impedance configurations at the data input during a first internal state of the integrated circuit device corresponding to the reception of write data on the data input, and causes the integrated circuit device to apply a second of the controllable termination impedance configurations at the data input during a second internal state of the integrated circuit device that follows the first internal state.
摘要翻译：控制部件向集成电路器件输出在集成电路器件的数据输入端施加多个可控终端阻抗配置中的一个的指示。所述指示使得所述集成电路装置在所述集成电路装置的第一内部状态期间在所述数据输入处施加第一可控终端阻抗配置，所述第一内部状态对应于所述数据输入上的写数据的接收，并且使所述集成电路装置在第一内部状态下的集成电路器件的第二内部状态期间，在数据输入端施加第二个可控终端阻抗配置。

8. 发明申请

US20110138133A1 Variable-Width Memory Module and Buffer 有权
标题翻译：可变宽度内存模块和缓冲区
公开(公告)号：US20110138133A1
公开(公告)日：2011-06-09
申请号：US12808662
申请日：2009-01-07
申请人： Ian P. Shaeffer
发明人： Ian P. Shaeffer
IPC分类号： G06F12/00
CPC分类号： G06F13/1678 , G06F13/1694
摘要： A memory module having a plurality of memory devices and a memory buffer that translates between a variable width primary data port and a plurality of fixed width secondary data ports, each of which is coupled to one of the memory devices. The translation is effected by distributing the width of the primary data port to all or to a subset of the secondary data ports. In another aspect, the invention comprises a memory buffer that supports adjustable data width in a variety of ways.
摘要翻译：具有多个存储器件的存储器模块和在可变宽度主数据端口和多个固定宽度辅助数据端口之间转换的存储器缓冲器，每个存储器模块耦合到存储器件之一。翻译是通过将主数据端口的宽度分配给所有或次要数据端口的子集来实现的。在另一方面，本发明包括以各种方式支持可调整数据宽度的存储器缓冲器。

9. 发明授权

US07602209B2 Controlling memory devices that have on-die termination 有权
标题翻译：控制具有片上终端的存储器件
公开(公告)号：US07602209B2
公开(公告)日：2009-10-13
申请号：US12199726
申请日：2008-08-27
申请人： Kyung Suk Oh , Ian P. Shaeffer
发明人： Kyung Suk Oh , Ian P. Shaeffer
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , G06F3/0605 , G06F3/0659 , G06F3/0685 , G06F13/4086 , G11C11/401 , G11C11/4063 , G11C11/4093 , G11C11/41 , G11C11/413 , G11C11/417 , G11C11/419 , G11C16/06 , G11C16/26 , G11C16/32 , H03K19/017545
摘要： A memory controller for controlling integrated circuit memory devices that have on-die termination. The memory controller includes an output driver to output a first data signal onto a data line, and termination control circuitry to output termination control signals to integrated circuit memory devices coupled to the data line. The termination control signals control coupling and decoupling of termination elements to the data line according to which of the plurality of integrated circuit memory devices is selected to receive the first data signal. In particular, the termination control signals specify coupling a termination element having an impedance indicated by a first termination value to the data line within one of the plurality of integrated circuit memory devices selected to receive the first data signal, and wherein the termination control signals further specify coupling a termination element having an impedance indicated by a second termination value to the data line within at least one other of the plurality of integrated circuit memory devices.
摘要翻译：一种用于控制具有片上终端的集成电路存储器件的存储器控制器。存储器控制器包括用于将第一数据信号输出到数据线上的输出驱动器，以及将终止控制信号输出到耦合到数据线的集成电路存储器件的终端控制电路。终止控制信号根据多个集成电路存储器件中的哪一个选择接收第一数据信号来控制终端元件到数据线的耦合和解耦。特别地，端接控制信号指定将具有由第一端接值指示的阻抗的终端元件耦合到被选择用于接收第一数据信号的多个集成电路存储器件中的一个内的数据线，并且其中终止控制信号进一步将具有由第二终止值指示的阻抗的终端元件指定到所述多个集成电路存储器件的至少另一个内的所述数据线。

10. 发明授权

US07558150B2 Memory controller with staggered request signal output 有权
标题翻译：具有交错请求信号输出的存储控制器
公开(公告)号：US07558150B2
公开(公告)日：2009-07-07
申请号：US11768107
申请日：2007-06-25
申请人： Ian P. Shaeffer , Bret Stott , Benedict C. Lau
发明人： Ian P. Shaeffer , Bret Stott , Benedict C. Lau
IPC分类号： G11C8/00
CPC分类号： G11C7/1063 , G06F12/00 , G06F13/1689 , G11C7/1072
摘要： A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
摘要翻译：具有时间交错请求信号输出的存储器控制器。根据第一编程值产生相对于第一时钟信号的相位偏移的第一定时信号，并且根据第二编程值产生相对于第一时钟信号的相位偏移的第二定时信号。响应于第一定时信号发送地址值，响应于构成第一存储器访问请求的第二定时信号，地址值和控制值发送控制值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式