专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06931573B2 Automated audit methodology for design 失效
标题翻译：设计自动审核方法
公开(公告)号：US06931573B2
公开(公告)日：2005-08-16
申请号：US09928604
申请日：2001-08-13
申请人： Janice M. Adams , Donald L. Hubbard , Jeannie H. Panner , Bruce D. Raymond
发明人： Janice M. Adams , Donald L. Hubbard , Jeannie H. Panner , Bruce D. Raymond
IPC分类号： G06F17/50 , G06F11/00
CPC分类号： G06F17/5022 , G06F17/5081
摘要： A method for design auditing by automating ways of auditing data produced by process steps is disclosed. The invention automates the process of auditing to account for complex methodology conditions. It also automates auditing of values of data produced by methodology steps. The invention provides a means of grouping task and information within a program and of preserving parent-child relationships.
摘要翻译：公开了一种通过自动化审计过程步骤产生的数据的方式进行设计审核的方法。本发明使审核过程自动化以解决复杂的方法条件。它还可以自动审核由方法步骤生成的数据的值。本发明提供了一种在程序内分组任务和信息以及保护父子关系的手段。

2. 发明授权

US07174486B2 Automation of fuse compression for an ASIC design system 失效
标题翻译：用于ASIC设计系统的熔断器压缩自动化
公开(公告)号：US07174486B2
公开(公告)日：2007-02-06
申请号：US10303444
申请日：2002-11-22
申请人： Janice M. Adams , Frank O. Distler , Mark F. Ollive , Michael R. Ouellette , Jeannie H. Panner
发明人： Janice M. Adams , Frank O. Distler , Mark F. Ollive , Michael R. Ouellette , Jeannie H. Panner
IPC分类号： G11C29/00
CPC分类号： G11C29/802 , H03K19/1735
摘要： A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.
摘要翻译：一种用于修复半导体芯片中的缺陷存储器的方法和系统。该芯片具有存储器位置，冗余存储器和用于有序保险丝的中心位置。有序保险丝以压缩格式识别存储器位置的缺陷部分。有缺陷的部分可由冗余存储器的部分替换。有序保险丝具有相关联的熔丝位模式，其顺序地表示压缩格式的缺陷部分。方法和系统确定存储器位置连接在一起的顺序; 根据存储器位置连接在一起的顺序，通过存储器位置设计锁存器的移位寄存器; 并且将每个锁存器与从其导出熔丝位模式的未压缩位模式的对应位相关联。未压缩比特模式包括一个比特序列，表示未压缩格式的缺陷部分。

3. 发明授权

US08024626B2 Automation of fuse compression for an ASIC design system 失效
标题翻译：用于ASIC设计系统的熔断器压缩自动化
公开(公告)号：US08024626B2
公开(公告)日：2011-09-20
申请号：US11552166
申请日：2006-10-24
申请人： Janice M. Adams , Frank O. Distler , Mark F. Ollive , Michael R. Ouellette , Jeannie H. Panner
发明人： Janice M. Adams , Frank O. Distler , Mark F. Ollive , Michael R. Ouellette , Jeannie H. Panner
IPC分类号： G11C29/00
CPC分类号： G11C29/802 , H03K19/1735
摘要： A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.
摘要翻译：一种用于修复半导体芯片中的有缺陷的存储器的方法和系统。该芯片具有存储器位置，冗余存储器和用于有序保险丝的中心位置。有序保险丝以压缩格式识别存储器位置的缺陷部分。有缺陷的部分可由冗余存储器的部分替换。有序保险丝具有相关联的熔丝位模式，其顺序地表示压缩格式的缺陷部分。方法和系统确定存储器位置连接在一起的顺序; 根据存储器位置连接在一起的顺序，通过存储器位置设计锁存器的移位寄存器; 并且将每个锁存器与从其导出熔丝位模式的未压缩位模式的对应位相关联。未压缩比特模式包括一个比特序列，表示未压缩格式的缺陷部分。

4. 发明授权

US06505324B1 Automated fuse blow software system 有权
标题翻译：自动保险丝熔断软件系统
公开(公告)号：US06505324B1
公开(公告)日：2003-01-07
申请号：US09680340
申请日：2000-10-05
申请人： Bruce Cowan , Frank O. Distler , Mark F. Ollive , Michael R. Ouellette , Jeannie H. Panner , Dora R. Pealer , Bruce D. Raymond , Paul S. Zuchowski
发明人： Bruce Cowan , Frank O. Distler , Mark F. Ollive , Michael R. Ouellette , Jeannie H. Panner , Dora R. Pealer , Bruce D. Raymond , Paul S. Zuchowski
IPC分类号： G06F1750
CPC分类号： G11C29/72 , G11C17/16 , G11C17/18 , G11C29/027 , G11C29/56 , G11C2029/5604 , G11C2029/5606
摘要： It is, therefore, an object of the present invention to provide a structure and method of blowing fuses in a semiconductor chip that includes creating a design for the chip using a library, generating test data from the design, extracting the fuse related information from the design to prepare a fuse blow table, building the chip with the design data, testing the chip to produce failed data, comparing the fuse blow table to the failed data to determine the fuse blow location data, and blowing the selected fuses based on the fuse blow location data. The extraction method can include creating a fuse map file based upon a correlation between physical pin locations on the chip and different fuse macros within the design, wherein an order of fuses within the fuse blow table matches an order of fuses within the fuse map file.
摘要翻译：因此，本发明的目的是提供一种在半导体芯片中熔断熔丝的结构和方法，该结构和方法包括使用库创建芯片的设计，从设计中产生测试数据，从熔丝相关信息中提取熔丝相关信息设计准备保险丝打火台，用设计数据构建芯片，测试芯片产生故障数据，比较保险丝熔断台与故障数据，确定保险丝熔断位置数据，并根据保险丝吹送选定的保险丝吹打位置数据。提取方法可以包括基于芯片上的物理引脚位置与设计中的不同熔丝宏之间的相关性来创建熔丝图文件，其中保险丝熔断台内的保险丝顺序与熔丝映射文件内的熔丝顺序匹配。

5. 发明授权

US06725439B1 Method of automated design and checking for ESD robustness 有权
标题翻译：自动设计和检查ESD鲁棒性的方法
公开(公告)号：US06725439B1
公开(公告)日：2004-04-20
申请号：US09678742
申请日：2000-10-04
申请人： Philip S. Homsinger , Andrew D. Huber , Debra K. Korejwa , William J. Livingstone , Jeannie H. Panner , Erich C. Schanzenbach , Douglas W. Stout , Steven H. Voldman , Paul S. Zuchowski
发明人： Philip S. Homsinger , Andrew D. Huber , Debra K. Korejwa , William J. Livingstone , Jeannie H. Panner , Erich C. Schanzenbach , Douglas W. Stout , Steven H. Voldman , Paul S. Zuchowski
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5077
摘要： A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a power supply or ground line, either directly or through an electrostatic discharge (ESD) protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or to return lines is also included. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection. Robust ESD protection is afforded all chip pads. The design may then be verified.
摘要翻译：具有ESD稳健性的集成电路（IC）芯片和IC芯片接线的系统和方法。每个芯片的I / O端口都应用最小导线宽度和最大电阻约束。这些限制被传播到设计中。阵列焊盘连接到位于芯片上的I / O单元。未使用或浮动焊盘可以直接或通过静电放电（ESD）保护装置连接到电源或接地线。还包括耦合在电源和接地或返回线路之间的多电源保护装置（ESDxx）。因此，布线使得ESD保护器件的导线和通孔足够宽，以提供足够的ESD保护。所有的芯片垫都提供了强大的ESD保护。然后可以验证设计。

6. 发明授权

US07096436B2 Macro design techniques to accommodate chip level wiring and circuit placement across the macro 有权
公开(公告)号：US07096436B2
公开(公告)日：2006-08-22
申请号：US10946552
申请日：2004-09-21
申请人： Thomas R. Bednar , Paul E. Dunn , Scott W. Gould , Jeannie H. Panner , Paul S. Zuchowski
发明人： Thomas R. Bednar , Paul E. Dunn , Scott W. Gould , Jeannie H. Panner , Paul S. Zuchowski
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , Y10S707/99931
摘要： Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one side of the macro to another; shielding using, for example, macro power bussing and/or macro wiring; routing power busses to the rearranged whitespace; and/or inserting active circuits with pins accessible to the wiring. In a preferred embodiment, active circuits are placed into rearranged macro whitespace during the design of subsequent stages. The rearrangement of the whitespace facilitates the wiring across the macro so that slew rate and path delay requirements of the subsequent stage wiring can be maintained, without excessive buffering or rerouting of wiring.

7. 发明授权

US06883155B2 Macro design techniques to accommodate chip level wiring and circuit placement across the macro 失效
公开(公告)号：US06883155B2
公开(公告)日：2005-04-19
申请号：US10403626
申请日：2003-03-31
申请人： Thomas R. Bednar , Paul E. Dunn , Scott W. Gould , Jeannie H. Panner , Paul S. Zuchowski
发明人： Thomas R. Bednar , Paul E. Dunn , Scott W. Gould , Jeannie H. Panner , Paul S. Zuchowski
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G06F17/5068 , Y10S707/99931
摘要： Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one side of the macro to another; shielding using, for example, macro power bussing and/or macro wiring; routing power busses to the rearranged whitespace; and/or inserting active circuits with pins accessible to the wiring. In a preferred embodiment, active circuits are placed into rearranged macro whitespace during the design of subsequent stages. The rearrangement of the whitespace facilitates the wiring across the macro so that slew rate and path delay requirements of the subsequent stage wiring can be maintained, without excessive buffering or rerouting of wiring.

8. 发明授权

US06543040B1 Macro design techniques to accommodate chip level wiring and circuit placement across the macro 有权
标题翻译：宏观设计技术，以适应芯片级布线和电路布局
公开(公告)号：US06543040B1
公开(公告)日：2003-04-01
申请号：US09526198
申请日：2000-03-15
申请人： Thomas R. Bednar , Paul E. Dunn , Scott W. Gould , Jeannie H. Panner , Paul S. Zuchowski
发明人： Thomas R. Bednar , Paul E. Dunn , Scott W. Gould , Jeannie H. Panner , Paul S. Zuchowski
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , Y10S707/99931
摘要： Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one side of the macro to another; shielding using, for example, macro power bussing and/or macro wiring; routing power busses to the rearranged whitespace; and/or inserting active circuits with pins accessible to the wiring. In a preferred embodiment, active circuits are placed into rearranged macro whitespace during the design of subsequent stages. The rearrangement of the whitespace facilitates the wiring across the macro so that slew rate and path delay requirements of the subsequent stage wiring can be maintained, without excessive buffering or rerouting of wiring.
摘要翻译：公开了宏观设计技术，以便于跨宏观的后续布线。重新布置宏中的空白区域以适应布线。重新布置可以采取将空白区域的物理重新布置成从宏的一侧延伸到另一侧的路由轨道的形式; 使用例如宏功率总线和/或宏布线进行屏蔽; 路由功率总线到重新排列的空格; 和/或插入具有可接线的引脚的有源电路。在优选实施例中，在后续阶段的设计期间，将有源电路放置在重排的宏空白中。空白的重新排列有助于宏观上的布线，使得可以保持后续级布线的压摆率和路径延迟要求，而不会过度缓冲或重新布线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式