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1. 发明授权

US08703578B2 Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations 有权
标题翻译：在28nm低功率/高性能技术上的PMOS器件的中间原位掺杂SiGe结，使用硅氧化物封装，早期晕圈和延伸注入
公开(公告)号：US08703578B2
公开(公告)日：2014-04-22
申请号：US13482410
申请日：2012-05-29
申请人： Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
发明人： Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
IPC分类号： H01L21/76
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/0883 , H01L29/0847 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO2 cap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.
摘要翻译：提供具有PMOS eSiGe源极/漏极区域的HKMG器件。实施例包括在衬底上形成第一和第二HKMG栅极堆叠，每个包括SiO 2盖，在第一HKMG栅极堆叠的相对侧形成延伸区域，在HKMG栅极堆叠的每一侧上形成氮化物衬垫和氧化物间隔物; 在第二个HKMG门堆栈上形成硬掩模; 在第一HKMG栅极堆叠的相对侧形成eSiGe，去除硬掩模，在第一和第二HKMG栅极堆叠中的每一个的氧化物间隔物上形成共形衬垫和氮化物间隔物，并且在第二HKMG栅堆叠的相对侧形成深源极/漏极区域第二个HKMG门栈。

2. 发明申请

US20130320449A1 LATE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS 有权
公开(公告)号：US20130320449A1
公开(公告)日：2013-12-05
申请号：US13482393
申请日：2012-05-29
申请人： Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
发明人： Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
IPC分类号： H01L21/8238 , H01L27/088 , H01L21/336
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L29/0847 , H01L29/1054 , H01L29/458 , H01L29/4925 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.

3. 发明申请

US20130320450A1 MIDDLE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS 有权
标题翻译：使用硅氧烷封装，早期黑曜石和延伸植入的28 NM低功率/高性能技术的PMOS器件的中间现场拨号信号连接
公开(公告)号：US20130320450A1
公开(公告)日：2013-12-05
申请号：US13482410
申请日：2012-05-29
申请人： Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
发明人： Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
IPC分类号： H01L27/088 , H01L21/8238 , H01L21/336
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/0883 , H01L29/0847 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO2 cap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.
摘要翻译：提供具有PMOS eSiGe源极/漏极区域的HKMG器件。实施例包括在衬底上形成第一和第二HKMG栅极堆叠，每个包括SiO 2盖，在第一HKMG栅极堆叠的相对侧形成延伸区域，在HKMG栅极堆叠的每一侧上形成氮化物衬垫和氧化物间隔物; 在第二个HKMG门堆栈上形成硬掩模; 在第一HKMG栅极堆叠的相对侧形成eSiGe，去除硬掩模，在第一和第二HKMG栅极堆叠中的每一个的氧化物间隔物上形成共形衬垫和氮化物间隔物，并在第二HKMG栅极叠层的相对侧形成深的源极/漏极区域第二个HKMG门栈。

4. 发明授权

US08936977B2 Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations 有权
标题翻译：在28nm低功率/高性能技术上使用硅氧化物封装，早期晕圈和延伸注入的PMOS器件的晚期原位掺杂SiGe结
公开(公告)号：US08936977B2
公开(公告)日：2015-01-20
申请号：US13482393
申请日：2012-05-29
申请人： Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
发明人： Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
IPC分类号： H01L21/338
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L29/0847 , H01L29/1054 , H01L29/458 , H01L29/4925 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.
摘要翻译：提供具有PMOS eSiGe源极/漏极区域的HKMG器件。实施例包括在衬底上形成第一和第二HKMG栅极堆叠，在每个HKMG栅极堆叠的每一侧上形成氮化物衬垫和氧化物衬垫，在每个HKMG栅极堆叠的每一侧执行卤素/延伸注入，形成氧化物衬垫和氮化物衬垫在每个HKMG栅极堆叠的氧化物间隔物上，在第二HKMG栅极堆叠的相对侧形成深的源极/漏极区域，在第二HKMG栅极堆叠层上形成氧化物硬掩模，在第一金属间化合物栅极堆叠的相对侧形成嵌入的硅锗（eSiGe） HKMG栅极堆叠，并去除氧化物硬掩模。

5. 发明申请

US20130095620A1 METHODS OF FORMING HIGHLY SCALED SEMICONDUCTOR DEVICES USING A DISPOSABLE SPACER TECHNIQUE 有权
标题翻译：使用可分散间隔技术形成高分辨率半导体器件的方法
公开(公告)号：US20130095620A1
公开(公告)日：2013-04-18
申请号：US13275766
申请日：2011-10-18
申请人： Jan Hoentschel , Stefan Flachowsky , Shiang Yang Ong
发明人： Jan Hoentschel , Stefan Flachowsky , Shiang Yang Ong
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823864
摘要： In one example, a method disclosed herein includes the steps of forming a first liner layer above a substrate and above gate structures for both a PMOS transistor and an NMOS transistor, and, after forming extension implant regions and halo implant regions, forming a first spacer proximate the gate structures of both the PMOS and NMOS transistors, forming deep source/drain implant regions in the substrate for the PMOS and NMOS transistors, removing the first spacer and, after removing the first spacer, forming a layer of material between the adjacent gate structures, wherein the layer of material occupies at least the space formerly occupied by the first spacer.
摘要翻译：在一个示例中，本文公开的方法包括以下步骤：在衬底上方形成第一衬垫层，并在PMOS晶体管和NMOS晶体管之上形成栅极结构之上，并且在形成扩展注入区域和晕圈注入区域之后，形成第一衬垫靠近PMOS和NMOS晶体管的栅极结构，在用于PMOS和NMOS晶体管的衬底中形成深源极/漏极注入区域，去除第一间隔物，并且在移除第一间隔物之后，在相邻栅极之间形成材料层结构，其中所述材料层至少占据由所述第一间隔件先前占据的空间。

6. 发明授权

US08440530B2 Methods of forming highly scaled semiconductor devices using a disposable spacer technique 有权
标题翻译：使用一次性间隔技术形成高度缩放的半导体器件的方法
公开(公告)号：US08440530B2
公开(公告)日：2013-05-14
申请号：US13275766
申请日：2011-10-18
申请人： Jan Hoentschel , Stefan Flachowsky , Shiang Yang Ong
发明人： Jan Hoentschel , Stefan Flachowsky , Shiang Yang Ong
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823864
摘要： In one example, a method disclosed herein includes the steps of forming a first liner layer above a substrate and above gate structures for both a PMOS transistor and an NMOS transistor, and, after forming extension implant regions and halo implant regions, forming a first spacer proximate the gate structures of both the PMOS and NMOS transistors, forming deep source/drain implant regions in the substrate for the PMOS and NMOS transistors, removing the first spacer and, after removing the first spacer, forming a layer of material between the adjacent gate structures, wherein the layer of material occupies at least the space formerly occupied by the first spacer.
摘要翻译：在一个示例中，本文公开的方法包括以下步骤：在衬底上方形成第一衬垫层，并在PMOS晶体管和NMOS晶体管之上形成栅极结构之上，并且在形成扩展注入区域和晕圈注入区域之后，形成第一衬垫靠近PMOS和NMOS晶体管的栅极结构，在用于PMOS和NMOS晶体管的衬底中形成深源极/漏极注入区域，去除第一间隔物，并且在移除第一间隔物之后，在相邻栅极之间形成材料层结构，其中所述材料层至少占据由所述第一间隔件先前占据的空间。

7. 发明授权

US09490344B2 Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process 有权
标题翻译：制造具有升高的源极/漏极区域的晶体管器件以适应金属硅化物形成过程中的消耗的方法
公开(公告)号：US09490344B2
公开(公告)日：2016-11-08
申请号：US13345922
申请日：2012-01-09
申请人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
发明人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L21/02 , H01L21/334 , H01L21/336 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66628 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7847 , H01L29/7848
摘要： Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. One illustrative method disclosed herein includes the steps of forming an upper portion of a source/drain region that is positioned above a surface of a semiconducting substrate, wherein the upper portion of the source/drain region has an upper surface that is positioned above the surface of the substrate by a distance that is at least equal to a target thickness of a metal silicide region to be formed in the upper portion of the source/drain region and forming the metal silicide region in the upper portion of the source/drain region.
摘要翻译：本文公开了具有双金属硅化物区域的各种半导体器件以及制造这种器件的各种方法。本文公开的一种说明性方法包括以下步骤：形成位于半导体衬底的表面上方的源极/漏极区的上部，其中源极/漏极区的上部具有位于表面上方的上表面以至少等于待形成在源/漏区上部的金属硅化物区域的目标厚度的距离，并在源/漏区的上部形成金属硅化物区域。

8. 发明授权

US08574981B2 Method of increasing the germanium concentration in a silicon-germanium layer and semiconductor device comprising same 有权
标题翻译：增加硅锗层中的锗浓度的方法和包括其的半导体器件的方法
公开(公告)号：US08574981B2
公开(公告)日：2013-11-05
申请号：US13101659
申请日：2011-05-05
申请人： Stefan Flachowsky , Thilo Scheiper , Peter Javorka , Jan Hoentschel
发明人： Stefan Flachowsky , Thilo Scheiper , Peter Javorka , Jan Hoentschel
IPC分类号： H01L21/02
CPC分类号： H01L21/02587 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/823807 , H01L21/84 , H01L29/1054 , H01L29/161 , H01L29/66431 , H01L29/66651 , H01L29/7781 , H01L29/7833
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming layer of silicon germanium on a P-active region of a semiconducting substrate wherein the layer of silicon germanium has a first concentration of germanium, and performing an oxidation process on the layer of silicon germanium to increase a concentration of germanium in at least a portion of the layer of silicon germanium to a second concentration that is greater than the first concentration of germanium.
摘要翻译：本文公开了形成半导体器件的方法。在一个示例中，该方法包括在半导体衬底的P活性区上形成硅锗层，其中硅锗层具有锗的第一浓度，并且在硅锗层上进行氧化处理以增加浓度在硅锗层的至少一部分中的锗至大于锗的第一浓度的第二浓度。

9. 发明授权

US08524563B2 Semiconductor device with strain-inducing regions and method thereof 有权
标题翻译：具有应变诱导区域的半导体器件及其方法
公开(公告)号：US08524563B2
公开(公告)日：2013-09-03
申请号：US13345457
申请日：2012-01-06
申请人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
发明人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/26586 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/7848
摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.
摘要翻译：通过引入应变诱导源极 - 漏极区域获得改进的MOSFET器件，其中栅极下方的最接近的“鼻”部分位于与器件表面不同的深度处。在优选实施例中，间隔开的源极 - 漏极区域可以横向重叠。这种接近度增加了应变诱导源 - 漏区对源极和漏极之间的感应沟道区域中的载流子迁移率的有利影响。源极 - 漏极区域通过外部重新填充从栅极的两侧蚀刻的不对称空洞形成。通过在栅极的仅一个侧壁附近形成初始腔，然后沿着预定的晶体方向蚀刻靠近栅极的两个侧壁的最后的间隔开的源极 - 漏极空腔来获得腔不对称性。具有不同高度的不同深度和鼻部区域的完成的腔体在栅极下彼此延伸，被外源重新填充用于源极 - 漏极区域的应变诱导半导体材料。

10. 发明授权

US08698243B2 Semiconductor device with strain-inducing regions and method thereof 有权
标题翻译：具有应变诱导区域的半导体器件及其方法
公开(公告)号：US08698243B2
公开(公告)日：2014-04-15
申请号：US13953349
申请日：2013-07-29
申请人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
发明人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L29/78 , H01L21/26586 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/7848
摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.
摘要翻译：通过引入应变诱导源极 - 漏极区域获得改进的MOSFET器件，其中栅极下方的最接近的“鼻”部分位于与器件表面不同的深度处。在优选实施例中，间隔开的源极 - 漏极区域可以横向重叠。这种接近度增加了应变诱导源 - 漏区对源极和漏极之间的感应沟道区域中的载流子迁移率的有利影响。源极 - 漏极区域通过外部重新填充从栅极的两侧蚀刻的不对称空洞形成。通过在栅极的仅一个侧壁附近形成初始腔，然后沿着预定的晶体方向蚀刻靠近栅极的两个侧壁的最后的间隔开的源极 - 漏极空腔来获得腔不对称性。具有不同高度的不同深度和鼻部区域的完成的腔体在栅极下彼此延伸，被外源重新填充用于源极 - 漏极区域的应变诱导半导体材料。

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