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1. 发明授权

US08458445B2 Compute units using local luts to reduce pipeline stalls 失效
标题翻译：计算单位使用本地的油脂来减少管道摊铺
公开(公告)号：US08458445B2
公开(公告)日：2013-06-04
申请号：US13206644
申请日：2011-08-10
申请人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Colm J. Prendergast , Gregory M. Yukna , Christopher M. Mayer
发明人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Colm J. Prendergast , Gregory M. Yukna , Christopher M. Mayer
IPC分类号： G06F9/44
CPC分类号： G06F9/3001 , G06F9/345 , G06F9/3885
摘要： Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.
摘要翻译：减少处理器中的计算单元和地址单元之间的流水线停顿可以通过响应于算法的指令在计算单元中计算结果来实现; 在计算单元中存储与本算法的预定指令集合的计算结果相关的预定函数集的局部随机存取存储器阵列; 并且在计算单元内提供计算结果与相关功能的直接映射。

2. 发明申请

US20110296145A1 PIPELINED DIGITAL SIGNAL PROCESSOR 失效
标题翻译：管道数字信号处理器
公开(公告)号：US20110296145A1
公开(公告)日：2011-12-01
申请号：US13206644
申请日：2011-08-10
申请人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Colm J. Prendergast , Gregory M. Yukna , Christopher M. Mayer
发明人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Colm J. Prendergast , Gregory M. Yukna , Christopher M. Mayer
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/345 , G06F9/3885
摘要： Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.
摘要翻译：减少处理器中的计算单元和地址单元之间的流水线停顿可以通过响应于算法的指令在计算单元中计算结果来实现; 在计算单元中存储与本算法的预定指令集合的计算结果相关的预定函数集的局部随机存取存储器阵列; 并且在计算单元内提供计算结果与相关功能的直接映射。

3. 发明授权

US08024551B2 Pipelined digital signal processor 有权
标题翻译：流水线数字信号处理器
公开(公告)号：US08024551B2
公开(公告)日：2011-09-20
申请号：US11258801
申请日：2005-10-26
申请人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Colm J. Prendergast , Gregory M. Yukna , Christopher M. Mayer
发明人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Colm J. Prendergast , Gregory M. Yukna , Christopher M. Mayer
IPC分类号： G06F9/00
CPC分类号： G06F9/3001 , G06F9/345 , G06F9/3885
摘要： Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.
摘要翻译：减少处理器中的计算单元和地址单元之间的流水线停顿可以通过响应于算法的指令在计算单元中计算结果来实现; 在计算单元中存储与本算法的预定指令集合的计算结果相关的预定函数集的局部随机存取存储器阵列; 并且在计算单元内提供计算结果与相关功能的直接映射。

4. 发明申请

US20090327378A1 Instruction-Based Parallel Median Filtering 有权
标题翻译：基于指令的并行中值滤波
公开(公告)号：US20090327378A1
公开(公告)日：2009-12-31
申请号：US12554500
申请日：2009-09-04
申请人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Gregory M. Yukna
发明人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Gregory M. Yukna
IPC分类号： G06F7/38 , G06F17/10
CPC分类号： G06F7/22 , G06F7/544 , G06F17/18 , H03H17/0263 , H03H2017/0298
摘要： An instruction-based parallel median filtering processor and method sorts in parallel each combination of pairs of inputs into greater and lesser values; determines from that sorting the minimum, maximum and median filter values of the inputs; processes one of those values and provides the processed value as an input; and applies an instruction for providing one of the values to the processing step, and at least one other instruction for enabling indication of at least one of the maximum, minimum, median filter values.
摘要翻译：基于指令的并行中值滤波处理器和方法将每组输入的输入并行分成更大和更小的值; 根据输入的最小值，最大值和中值滤波器值进行排序; 处理这些值之一并将处理的值提供为输入; 并且向所述处理步骤应用用于提供所述值中的一个的指令，以及用于使得能够指示所述最大值，最小中值滤波器值中的至少一个的至少一个其他指令。

5. 发明授权

US08321490B2 Instruction-based parallel median filtering 有权
标题翻译：基于指令的并行中值滤波
公开(公告)号：US08321490B2
公开(公告)日：2012-11-27
申请号：US12554500
申请日：2009-09-04
申请人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Gregory M. Yukna
发明人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Gregory M. Yukna
IPC分类号： G06F17/10 , G06F7/00
CPC分类号： G06F7/22 , G06F7/544 , G06F17/18 , H03H17/0263 , H03H2017/0298
摘要： An instruction-based parallel median filtering processor and method sorts in parallel each combination of pairs of inputs into greater and lesser values; determines from that sorting the minimum, maximum and median filter values of the inputs; processes one of those values and provides the processed value as an input; and applies an instruction for providing one of the values to the processing step, and at least one other instruction for enabling indication of at least one of the maximum, minimum, median filter values.
摘要翻译：基于指令的并行中值滤波处理器和方法将每组输入的输入并行分成更大和更小的值; 根据输入的最小值，最大值和中值滤波器值进行排序; 处理这些值中的一个并将处理的值提供为输入; 并且向所述处理步骤应用用于提供所述值中的一个的指令，以及用于使得能够指示所述最大值，最小中值滤波器值中的至少一个的至少一个其他指令。

6. 发明授权

US08285972B2 Lookup table addressing system and method 有权
标题翻译：查找表寻址系统和方法
公开(公告)号：US08285972B2
公开(公告)日：2012-10-09
申请号：US11258662
申请日：2005-10-26
申请人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Christopher M. Mayer
发明人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Christopher M. Mayer
IPC分类号： G06F9/34
CPC分类号： G06F9/30018 , G06F9/3004 , G06F9/345 , G06F9/3552 , G09C1/00 , H04L9/06 , H04L2209/122
摘要： Lookup table addressing of a set of lookup tables in an external memory is achieved by: transferring a data word from a compute unit to an input register in a data address generator; providing in at least one deposit-increment index register in the data address generator including a table base field for identifying the location of the set of tables in memory, and a displacement field; and depositing a section of the data word into a displacement field in the index register for identifying the location of a specific entry in the tables.
摘要翻译：通过以下方式实现外部存储器中的一组查找表的查找表寻址：将数据字从计算单元传送到数据地址生成器中的输入寄存器; 在数据地址生成器中的至少一个存储增量索引寄存器中提供包括用于识别存储器中的一组表的位置的表基字段和位移字段; 以及将所述数据字的一部分存储在所述索引寄存器中的位移字段中，以用于识别所述表中的特定条目的位置。

7. 发明授权

US07498960B2 Programmable compute system for executing an H.264 binary decode symbol instruction 有权
标题翻译：用于执行H.264二进制解码符号指令的可编程计算系统
公开(公告)号：US07498960B2
公开(公告)日：2009-03-03
申请号：US11788094
申请日：2007-04-19
申请人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Christopher M. Mayer
发明人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Christopher M. Mayer
IPC分类号： H03M7/00
CPC分类号： H03M7/4006
摘要： A compute system for executing an h.264 binary decode symbol instruction including a first compute unit having a range normalization circuit and an rLPS update circuit, and operating in a first mode responsive to current rLPS, range, value and current context to generate the next normalized range and next rLPS for the current context; a second compute unit including a value update circuit, a context update circuit, and value normalization circuit responsive to current rLPS, range value and current context to obtain the output bit, normalized value and the updated current context; and a third compute unit or said first compute unit operating in a second mode including a range circuit and a next context rLPS circuit responsive to rLPS range, value and next context to obtain a next context rLPS value.
摘要翻译：一种用于执行h.264二进制解码符号指令的计算系统，包括具有范围归一化电路和rLPS更新电路的第一计算单元，并且响应于当前的rLPS，范围，值和当前上下文以第一模式操作以产生下一个标准化范围和下一个rLPS为当前上下文; 第二计算单元，包括响应于当前rLPS，范围值和当前上下文的值更新电路，上下文更新电路和值归一化电路，以获得输出位，归一化值和更新的当前上下文; 以及第三计算单元或所述第一计算单元，其以第二模式操作，包括响应于rLPS范围，值和下一个上下文的范围电路和下一个上下文rLPS电路，以获得下一个上下文rLPS值。

8. 发明申请

US20080258947A1 Programmable compute system for executing an H.264 binary decode symbol instruction 有权
标题翻译：用于执行H.264二进制解码符号指令的可编程计算系统
公开(公告)号：US20080258947A1
公开(公告)日：2008-10-23
申请号：US11788094
申请日：2007-04-19
申请人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Christopher M. Mayer
发明人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Christopher M. Mayer
IPC分类号： H03M7/00
CPC分类号： H03M7/4006
摘要： A compute system for executing an h.264 binary decode symbol instruction including a first compute unit having a range normalization circuit and an rLPS update circuit, and operating in a first mode responsive to current rLPS, range, value and current context to generate the next normalized range and next rLPS for the current context; a second compute unit including a value update circuit, a context update circuit, and value normalization circuit responsive to current rLPS, range value and current context to obtain the output bit, normalized value and the updated current context; and a third compute unit or said first compute unit operating in a second mode including a range circuit and a next context rLPS circuit responsive to rLPS range, value and next context to obtain a next context rLPS value.
摘要翻译：一种用于执行h.264二进制解码符号指令的计算系统，包括具有范围归一化电路和rLPS更新电路的第一计算单元，并且响应于当前的rLPS，范围，值和当前上下文以第一模式操作以产生下一个标准化范围和下一个rLPS为当前上下文; 第二计算单元，包括响应于当前rLPS，范围值和当前上下文的值更新电路，上下文更新电路和值归一化电路，以获得输出位，归一化值和更新的当前上下文; 以及第三计算单元或所述第一计算单元，其以第二模式操作，包括响应于rLPS范围，值和下一个上下文的范围电路和下一个上下文rLPS电路，以获得下一个上下文rLPS值。

9. 发明申请

US20080075376A1 Iterative process with rotated architecture for reduced pipeline dependency 审中-公开
标题翻译：具有旋转架构的迭代过程，以减少管道依赖性
公开(公告)号：US20080075376A1
公开(公告)日：2008-03-27
申请号：US11527001
申请日：2006-09-26
申请人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Christopher M. Mayer
发明人： James Wilson , Joshua A. Kablotsky , Yosef Stein , Christopher M. Mayer
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： H04N19/436 , H04N19/13 , H04N19/61
摘要： In a pipeline machine where, in an iterative process, one or more subsequent functions employ one or more parameters determined by one or more antecedent functions and the one or more subsequent functions generate one or more parameters for the one or more antecedent functions, pipeline dependency is reduced by advancing or rotating the iterative process by preliminarily providing to the subsequent function the next one or more parameters on which it is dependent and thereafter: generating by the subsequent function, in response to the one or more parameters on which is it dependent, the next one or more parameters required by the one or more antecedent functions and then, generating by the one or more antecedent functions, in response to the one or more parameters required by the one or more antecedent functions, the next one or more parameters for input to the subsequent function for the next iteration.
摘要翻译：在管线机器中，其中在迭代过程中，一个或多个后续功能采用由一个或多个先行函数确定的一个或多个参数，并且所述一个或多个后续函数为一个或多个先行函数生成一个或多个参数，流水线依赖通过预先向随后的功能提供下一个或多个依赖于其的参数，然后：通过随后的功能生成响应于依赖于其的一个或多个参数，推进或旋转迭代过程，所述一个或多个先行函数所需的下一个或多个参数，然后响应于所述一个或多个先行函数所需的一个或多个参数，由一个或多个先行函数生成下一个或多个参数，用于输入下一次迭代的后续功能。

10. 发明授权

US07882284B2 Compute unit with an internal bit FIFO circuit 有权
标题翻译：具有内部位FIFO电路的计算单元
公开(公告)号：US07882284B2
公开(公告)日：2011-02-01
申请号：US11728358
申请日：2007-03-26
申请人： James Wilson , Yosef Stein , Joshua A. Kablotsky
发明人： James Wilson , Yosef Stein , Joshua A. Kablotsky
IPC分类号： G06F3/00 , G06F5/00 , G11C7/10
CPC分类号： G06F5/10 , G06F5/00 , G06F5/065 , G06F5/14 , G06F9/30018 , G06F9/3824 , G06F2205/126
摘要： A compute unit with an internal bit FIFO circuit includes at least one data register, a lookup table, a configuration register including FIFO base address, length and read/write mode fields for configuring a portion of the lookup table as a bit FIFO circuit and a read/write pointer register responsive to an instruction having a lookup table identification field, length of bits field and register extract/deposit field for selectively transferring in a single cycle between the FIFO circuit and the data register a bit field of specified length.
摘要翻译：具有内部位FIFO电路的计算单元包括至少一个数据寄存器，查找表，包括用于将查找表的一部分配置为位FIFO电路的FIFO基址，长度和读/写模式字段的配置寄存器，以及读/写指针寄存器响应于具有查找表识别字段，位字段长度和寄存器提取/存储字段的指令，用于在FIFO电路和数据寄存器之间的单个周期中选择性地传送具有指定长度的位字段。

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