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1. 发明授权

US07606050B2 Compact module system and method 有权
标题翻译：紧凑型模块系统和方法
公开(公告)号：US07606050B2
公开(公告)日：2009-10-20
申请号：US11187269
申请日：2005-07-22
申请人： James W. Cady , James Douglas Wehrly, Jr. , Paul Goodwin
发明人： James W. Cady , James Douglas Wehrly, Jr. , Paul Goodwin
IPC分类号： H05K7/00
CPC分类号： H05K1/189 , H05K2201/056 , H05K2201/10159 , H05K2201/10189
摘要： A flexible circuit is populated on one or both sides and disposed about a substrate to create a circuit module. Along one of its edges, the flex circuit is connected to a connective facility such as a multiple pin connector while the flex circuit is disposed about a thermally-conductive form that provides structure to create a module with plural layers of circuitry in a single module. In preferred embodiments, the form is metallic and, in alternative preferred embodiments, the module circuitry is disposed within a housing. Preferred embodiments may be devised that present a compact flash module within a housing that may be connected to or into a system or product through a connective facility that is preferably a male or female socket connector while the housing is configured to mechanically adapt to an application environment.
摘要翻译：柔性电路填充在一侧或两侧并且设置在基板周围以形成电路模块。沿着其边缘之一，柔性电路连接到诸如多针连接器的连接设备，而柔性电路围绕导热形式设置，其提供结构以在单个模块中创建具有多层电路的模块。在优选实施例中，该形式是金属的，并且在替代优选实施例中，模块电路设置在壳体内。可以设计出优选实施例，其在壳体内呈现紧凑型闪光模块，其可以通过连接设备连接到系统或产品，该连接设备优选地是公插座或母插座连接器，而壳体被配置为机械地适应应用环境。

2. 发明授权

US07542304B2 Memory expansion and integrated circuit stacking system and method 有权
标题翻译：内存扩展和集成电路堆叠系统及方法
公开(公告)号：US07542304B2
公开(公告)日：2009-06-02
申请号：US10804452
申请日：2004-03-19
申请人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle
发明人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle
IPC分类号： H01R9/00
CPC分类号： H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/107 , H01L2924/3011 , H01L2924/00012
摘要： The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.
摘要翻译：本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。在根据本发明的优选实施例中，形式标准提供了一种物理形式，其允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计时被有利地使用。在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。在存储器寻址系统的优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载影响。

3. 发明授权

US07202555B2 Pitch change and chip scale stacking system and method 有权
标题翻译：间距变换和芯片级堆叠系统及方法
公开(公告)号：US07202555B2
公开(公告)日：2007-04-10
申请号：US11074026
申请日：2005-03-08
申请人： David L. Roper , James W. Cady , James Wilder , James Douglas Wehrly, Jr. , Jeff Buchle , Julian Dowden
发明人： David L. Roper , James W. Cady , James Wilder , James Douglas Wehrly, Jr. , Jeff Buchle , Julian Dowden
IPC分类号： H01L23/02
CPC分类号： H01L23/49816 , H01L23/3114 , H01L23/49827 , H01L23/4985 , H01L23/5386 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/0002 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/058 , H05K2201/10734 , H01L2924/0001
摘要： The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and its application environment. The module has a bailout pattern with a different pitch and/or supplemental module contacts devised to allow combined signaling to the integrated circuits through contacts having a desired ballout footprint. The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.
摘要翻译：本发明将集成电路堆叠成节省电路板表面积的模块。在根据本发明的优选实施例设计的两高堆叠或模块中，堆叠一对集成电路，一个集成电路在另一个之上。两个集成电路与一对柔性电路结构连接。一对柔性电路结构中的每一个部分地缠绕在模块的下部集成电路的相应的相对侧边缘上。柔性电路对连接上下集成电路，并在模块与其应用环境之间提供热和电路连接路径。该模块具有一个具有不同间距和/或补充模块触点的救援模式，用于允许通过具有期望的展开足迹的触点对集成电路的组合信令。本发明可以有利于提供用于高密度存储器或高容量计算的模块中的集成电路的多种配置和组合。

4. 发明授权

US07586758B2 Integrated circuit stacking system 有权
标题翻译：集成电路堆叠系统
公开(公告)号：US07586758B2
公开(公告)日：2009-09-08
申请号：US10958924
申请日：2004-10-05
申请人： James W. Cady , James Wilder , David L. Roper , Russell Rapport , James Douglas Wehrly, Jr. , Jeffrey Alan Buchle
发明人： James W. Cady , James Wilder , David L. Roper , Russell Rapport , James Douglas Wehrly, Jr. , Jeffrey Alan Buchle
IPC分类号： H05K1/11 , H05K1/14
CPC分类号： H01L23/49816 , H01L23/3114 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2225/1094 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00012
摘要： The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP integrated circuit and a support element CSP integrated circuit are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint. The flex circuit provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).
摘要翻译：本发明将封装的集成电路堆叠成节省PWB或其他板表面积的模块。本发明可以利用各种尺寸和配置的封装，其范围从具有许多触点的较大封装的基底元件到较小的封装，例如诸如DSBGA的裸片尺寸的封装。在根据本发明设计的优选实施例中，基体元件CSP集成电路和支撑元件CSP集成电路通过具有图案化以选择性地连接两个CSP元件的至少两个导电层的柔性电路聚集。连接到支撑元件的柔性电路的一部分折叠在基座元件上，以将支撑元件设置在基座元件上方，同时减小了总的占地面积。柔性电路在模块和诸如印刷电路板（PWB）的应用环境之间提供热和电连接路径。

5. 发明授权

US07495334B2 Stacking system and method 有权
标题翻译：堆叠系统和方法
公开(公告)号：US07495334B2
公开(公告)日：2009-02-24
申请号：US11197267
申请日：2005-08-04
申请人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle , Julian Dowden
发明人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle , Julian Dowden
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/50 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/15173 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/0401
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the other. The two CSPs are connected with flex circuitry. A form standard is disposed between the flex circuitry and a CSP in the stack. The form standard can take many configurations and may be used where flex circuits are used to connect CSPs to one another in stacked modules having two or more constituent CSPs. For example, in stacked modules that include four CSPs, three form standards are employed in preferred embodiments, although fewer may be used. The form standard provides a thermally conductive physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.
摘要翻译：本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。在根据本发明的优选实施例设计的两高CSP堆叠或模块中，堆叠两个CSP，其中一个CSP设置在另一个之上。两个CSP与柔性电路连接。在柔性电路和堆叠中的CSP之间设置一个形式标准。形式标准可以采用许多配置，并且可以在柔性电路用于在具有两个或更多个组成CSP的堆叠模块中将CSP彼此连接的位置中使用。例如，在包括四个CSP的堆叠模块中，在优选实施例中采用三个形式标准，尽管可以使用更少的标准。形式标准提供导热物理形式，允许在广泛的CSP封装系列中找到许多变化的封装尺寸，同时采用标准连接柔性电路设计。

6. 发明授权

US07335975B2 Integrated circuit stacking system and method 有权
标题翻译：集成电路堆叠系统及方法
公开(公告)号：US07335975B2
公开(公告)日：2008-02-26
申请号：US10958934
申请日：2004-10-05
申请人： James W. Cady , James Wilder , David L. Roper , Russell Rapport , James Douglas Wehrly, Jr. , Jeffrey Alan Buchle
发明人： James W. Cady , James Wilder , David L. Roper , Russell Rapport , James Douglas Wehrly, Jr. , Jeffrey Alan Buchle
IPC分类号： H01L23/48
CPC分类号： H01L23/49816 , H01L23/3114 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2225/1094 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00012
摘要： The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP and a support element CSP are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. The flex circuit connects the ICs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).
摘要翻译：本发明将封装的集成电路堆叠成节省PWB或其他板表面积的模块。本发明提供了用于将芯片级封装集成电路（CSP）或具有其他CSP的引线封装或者将单片或堆叠引线封装集成到节省PWB或其他板表面积的模块中的技术和结构。本发明可以利用各种尺寸和配置的封装，其范围从具有许多触点的较大封装的基底元件到较小的封装，例如诸如DSBGA的裸片尺寸的封装。在根据本发明设计的优选实施例中，基体元件CSP和支撑元件CSP通过具有图案化以选择性地连接两个CSP元件的至少两个导电层的柔性电路聚集。柔性电路连接IC，并在模块和诸如印刷电路板（PWB）的应用环境之间提供热和电连接路径。

7. 发明授权

US06956284B2 Integrated circuit stacking system and method 有权
标题翻译：集成电路堆叠系统及方法
公开(公告)号：US06956284B2
公开(公告)日：2005-10-18
申请号：US10814532
申请日：2004-03-31
申请人： James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
发明人： James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
IPC分类号： H01L23/02 , H01L23/31 , H01L23/367 , H01L23/498 , H01L23/538 , H01L25/10 , H05K1/14 , H05K1/18 , H05K3/36
CPC分类号： H01L23/3114 , H01L23/4985 , H01L23/5386 , H01L23/5387 , H01L25/105 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/06589 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/16225 , H01L2924/00012 , H01L2224/0401
摘要： The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard may include a heat spreader portion with mounting feet. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.
摘要翻译：本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。在根据本发明的优选实施例中，形式标准提供了一种物理形式，其允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计时被有利地使用。在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。在替代实施例中，形式标准可以包括具有安装支脚的散热器部分。在存储器寻址系统的优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载影响。

8. 发明授权

US06576992B1 Chip scale stacking system and method 有权
标题翻译：芯片级堆叠系统及方法
公开(公告)号：US06576992B1
公开(公告)日：2003-06-10
申请号：US10005581
申请日：2001-10-26
申请人： James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Julian Dowden , Jeff Buchle
发明人： James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Julian Dowden , Jeff Buchle
IPC分类号： H05K706
CPC分类号： H05K1/141 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/01087 , H01L2924/19041 , H01L2924/3011 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, a pair of CSPs is stacked, with one CSP above the other. The two CSPs are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower CSP of the module. The flex circuit pair connects the upper and lower CSPs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of CSPs in modules provided for high-density memories or high capacity computing.
摘要翻译：本发明将芯片级封装集成电路（CSP）堆叠成节省板表面积的模块。在根据本发明的优选实施例设计的两高CSP堆栈或模块中，堆叠一对CSP，其中一个CSP在另一CSP之上。两个CSP与一对柔性电路结构连接。一对柔性电路结构中的每一个部分地围绕模块的下CSP的相应的相对侧边缘缠绕。柔性电路对连接上部和下部CSP，并且在模块和诸如印刷线路板（PWB）的应用环境之间提供热和电连接路径。本发明可以有利于提供用于高密度存储器或高容量计算的模块中的CSP的多种配置和组合。

9. 发明授权

US07626273B2 Low profile stacking system and method 有权
标题翻译：薄型堆叠系统和方法
公开(公告)号：US07626273B2
公开(公告)日：2009-12-01
申请号：US12356432
申请日：2009-01-20
申请人： Julian Partridge , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
发明人： Julian Partridge , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
IPC分类号： H01L23/538
CPC分类号： H01L25/0657 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/105 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/13116 , H01L2224/16237 , H01L2224/73253 , H01L2224/81011 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/3463 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00
摘要： The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.
摘要翻译：本发明提供了一种将集成电路器件安装到衬底上的系统和方法，以及用于将堆叠模块中采用该方法的系统和方法。封装的集成电路器件的接触焊盘基本上露出。将包括较高温度的焊膏合金的焊膏施加到要安装的基板或集成电路器件上。集成电路器件定位成与衬底的触点接触。施加热量以在基板的触点和集成电路装置之间形成高温接头，从而形成具有高温接头的装置 - 基板组件。形成的接头在随后的加工步骤中较少受到再熔化。该方法可以用于设计堆叠的模块结构，例如根据本发明的优选实施例中公开的那些。通常，创建的关节的轮廓较低。

10. 发明授权

US07524703B2 Integrated circuit stacking system and method 有权
标题翻译：集成电路堆叠系统及方法
公开(公告)号：US07524703B2
公开(公告)日：2009-04-28
申请号：US11221597
申请日：2005-09-07
申请人： James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
发明人： James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
IPC分类号： H01L21/00
CPC分类号： H01L23/3114 , H01L23/4985 , H01L23/5386 , H01L23/5387 , H01L25/105 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/06589 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/16225 , H01L2924/00012 , H01L2224/0401
摘要： The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard may include a heat spreader portion with mounting feet. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.
摘要翻译：本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。在根据本发明的优选实施例中，形式标准提供了一种物理形式，其允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计时被有利地使用。在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。在替代实施例中，形式标准可以包括具有安装支脚的散热器部分。在存储器寻址系统的优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载影响。

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