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1. 发明授权

US07459360B2 Method of forming pixel sensor cell having reduced pinning layer barrier potential 有权
标题翻译：形成具有降低的钉扎层势垒势垒的像素传感器单元的方法
公开(公告)号：US07459360B2
公开(公告)日：2008-12-02
申请号：US11681454
申请日：2007-03-02
申请人： James W. Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Jerome B. Lasky , Richard A. Phelps
发明人： James W. Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Jerome B. Lasky , Richard A. Phelps
IPC分类号： H01L21/8238
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A method of forming a pixel sensor cell structure. The method of forming the pixel cell comprises forming a doped layer adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：一种形成像素传感器单元结构的方法。形成像素单元的方法包括形成与传输栅极结构的第一侧相邻的掺杂层，用于耦合收集阱区和沟道区。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

2. 发明授权

US07205591B2 Pixel sensor cell having reduced pinning layer barrier potential and method thereof 有权
标题翻译：具有降低的钉扎层势垒势的像素传感器单元及其方法
公开(公告)号：US07205591B2
公开(公告)日：2007-04-17
申请号：US10907570
申请日：2005-04-06
申请人： James W. Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Jerome B Lasky , Richard A. Phelps
发明人： James W. Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Jerome B Lasky , Richard A. Phelps
IPC分类号： H01L27/148
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

3. 发明授权

US07217968B2 Recessed gate for an image sensor 有权
标题翻译：嵌入式门用于图像传感器
公开(公告)号：US07217968B2
公开(公告)日：2007-05-15
申请号：US10905097
申请日：2004-12-15
申请人： James W. Adkisson , John Ellis-Monaghan , Mark D. Jaffe , Jerome B. Lasky
发明人： James W. Adkisson , John Ellis-Monaghan , Mark D. Jaffe , Jerome B. Lasky
IPC分类号： H01L31/062
CPC分类号： H01L27/14603 , H01L27/14601 , H01L27/14689 , H01L29/66621
摘要： A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.
摘要翻译：一种新颖的图像传感器单元结构及其制造方法。成像传感器包括基板，包括电介质层和形成在电介质层上的栅极导体的栅极，形成在与栅极导体的第一侧相邻的基板的表面下面的第一导电类型的收集阱层，钉扎层在基板表面上形成在集合阱顶部的第二导电类型的第一导电类型的扩散区和在栅极导体的第二侧附近形成的第一导电类型的扩散区，栅极导体在集电阱层和扩散区之间形成沟道区。栅极导体底部的一部分凹陷在基板的表面下方。优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到使得收集阱与沟道区相交的深度。

4. 发明授权

US07572701B2 Recessed gate for a CMOS image sensor 有权
标题翻译： CMOS图像传感器的嵌入式门
公开(公告)号：US07572701B2
公开(公告)日：2009-08-11
申请号：US11735223
申请日：2007-04-13
申请人： James W. Adkisson , John Ellis-Monaghan , Mark D. Jaffe , Jerome B. Lasky
发明人： James W. Adkisson , John Ellis-Monaghan , Mark D. Jaffe , Jerome B. Lasky
IPC分类号： H01L21/02 , H01L31/113
CPC分类号： H01L27/14603 , H01L27/14601 , H01L27/14689 , H01L29/66621
摘要： A novel CMOS image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate having an upper surface, a gate comprising a dielectric layer formed on the substrate and a gate conductor formed on the gate dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. A portion of the bottom of the gate conductor is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region thereby eliminating any potential barrier interference caused by the pinning layer.
摘要翻译：一种新颖的CMOS图像传感器单元结构及其制造方法。成像传感器包括具有上表面的基板，包括形成在基板上的电介质层的栅极和形成在栅极电介质层上的栅极导体，形成在基板表面附近的第一导电类型的集合阱层栅极导体的第一侧，形成在基板表面上的集电阱顶部的第二导电类型的钉扎层，以及邻近栅极导体的第二侧形成的第一导电类型的扩散区域，栅极导体形成沟道收集阱层和扩散区域之间的区域。栅极导体的底部的一部分在衬底的表面下方凹进。优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到深度，使得收集阱与沟道区相交，从而消除由钉扎层引起的任何潜在的屏障干扰。

5. 发明授权

US09058455B2 Backside integration of RF filters for RF front end modules and design structure 有权
标题翻译：用于RF前端模块的RF滤波器的背面集成和设计结构
公开(公告)号：US09058455B2
公开(公告)日：2015-06-16
申请号：US13354705
申请日：2012-01-20
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： G06F17/50 , H01L21/768 , H01L23/48 , H03H9/64 , H01L23/00 , H01L27/06 , H01L49/02 , H01L23/66 , H01L25/16
CPC分类号： H01L41/293 , G06F17/5063 , G06F17/5068 , H01L21/76898 , H01L23/481 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/24 , H01L25/16 , H01L27/0694 , H01L28/40 , H01L41/0815 , H01L41/25 , H01L2224/03009 , H01L2224/0401 , H01L2224/04105 , H01L2224/0557 , H01L2224/05572 , H01L2224/06181 , H01L2224/12105 , H01L2224/14181 , H01L2224/16145 , H01L2224/24145 , H01L2225/06548 , H03H9/64
摘要： A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.
摘要翻译：在半导体衬底的背面上的集成射频（RF）滤波器的设计结构包括：在衬底的第一侧上的器件; 在衬底的背面上的射频（RF）滤波器; 以及至少一个衬底导体，其从所述衬底的前侧延伸到所述衬底的所述背面并将所述RF滤波器电耦合到所述器件。

6. 发明授权

US07772028B2 CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom 失效
标题翻译：具有Cu布线的CMOS成像器和从其中消除高反射率界面的方法
公开(公告)号：US07772028B2
公开(公告)日：2010-08-10
申请号：US11959841
申请日：2007-12-19
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel , Anthony K. Stamper
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel , Anthony K. Stamper
IPC分类号： H01L21/66
CPC分类号： H01L27/14636 , H01L21/76819 , H01L21/76834 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14629 , H01L27/14645 , H01L27/14683
摘要： A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.
摘要翻译： CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

7. 发明授权

US07655495B2 Damascene copper wiring optical image sensor 有权
标题翻译：大马士革铜线接线光学图像传感器
公开(公告)号：US07655495B2
公开(公告)日：2010-02-02
申请号：US11623977
申请日：2007-01-17
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Anthony K. Stamper
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： H01L27/14685 , H01L21/76819 , H01L21/76834 , H01L21/76838 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14687
摘要： A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.
摘要翻译： CMOS图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合更薄的层间电介质叠层，具有改进的厚度均匀性，以产生呈现增加的光敏度的像素阵列。在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。然后将蚀刻的开口用电介质材料重新填充。在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

8. 发明授权

US07521798B2 Stacked imager package 有权
标题翻译：堆叠成像器包
公开(公告)号：US07521798B2
公开(公告)日：2009-04-21
申请号：US11943277
申请日：2007-11-20
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L23/48
CPC分类号： H01L27/14618 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/13091 , H01L2924/15151 , H01L2924/00014 , H01L2924/00
摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.
摘要翻译：用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。互连装置提供例如与手机的空间限制相匹配的CSP。该布置还利用最小的线长度来降低噪声。将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

9. 发明授权

US07361581B2 High surface area aluminum bond pad for through-wafer connections to an electronic package 有权
标题翻译：高表面积铝合金焊盘，用于通过晶片连接到电子封装
公开(公告)号：US07361581B2
公开(公告)日：2008-04-22
申请号：US10904677
申请日：2004-11-23
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L21/44
CPC分类号： H01L24/02 , H01L23/3114 , H01L23/481 , H01L2224/0401 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/3011 , H01L2924/00
摘要： A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.
摘要翻译：用于实现通过晶片连接到集成电路或电子封装的接合焊盘及其制造方法。接合焊盘包括高表面积铝键合焊盘，以便得到接合焊盘和电引线之间的高度可靠的低电阻连接。

10. 发明授权

US08723392B2 Saw filter having planar barrier layer and method of making 有权
标题翻译：具有平面阻挡层的锯片和制造方法
公开(公告)号：US08723392B2
公开(公告)日：2014-05-13
申请号：US13183977
申请日：2011-07-15
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： H03H9/25
CPC分类号： H03H9/14538 , H03H3/08
摘要： Disclosed herein is a surface acoustic wave (SAW) filter and method of making the same. The SAW filter includes a piezoelectric substrate; a planar barrier layer disposed above the piezoelectric substrate, and at least one conductor buried in the piezoelectric substrate and the planar barrier layer.
摘要翻译：本文公开了一种表面声波（SAW）滤波器及其制造方法。 SAW滤波器包括压电基片; 设置在所述压电基板上方的平面阻挡层，以及埋设在所述压电基板和所述平面阻挡层中的至少一个导体。

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