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1. 发明申请

US20070090887A1 Lock detect circuit for a phase locked loop 有权
标题翻译：用于锁相环路的锁定检测电路
公开(公告)号：US20070090887A1
公开(公告)日：2007-04-26
申请号：US11254569
申请日：2005-10-20
申请人： James Seefeldt , Bradley Kantor
发明人： James Seefeldt , Bradley Kantor
IPC分类号： H03L7/00
CPC分类号： H03D13/004 , H03L7/095 , Y10S331/02
摘要： An improved system and method for determining the lock condition of a Phase Locked Loop (PLL) is described. The lock detect circuit generates a fast lock detect signal that may be used to detect a transient loss of lock. The lock detect circuit may also include a phase alignment detect circuit to detect a misalignment in the phase of a reference clock and a feedback clock. Additionally, the lock detect circuit may include a reference clock detect circuit to detect if the reference clock signal is detected. Output signals from all of the above circuits may be communicated to a logic circuit in order to create an enhanced lock detect signal. An extended lock detect signal may also be communicated to the logic circuit.
摘要翻译：描述了用于确定锁相环（PLL）的锁定状态的改进的系统和方法。锁定检测电路产生快速锁定检测信号，其可用于检测瞬时的锁定损失。锁定检测电路还可以包括相位对准检测电路，用于检测参考时钟和反馈时钟的相位中的未对准。此外，锁定检测电路可以包括参考时钟检测电路，以检测是否检测到参考时钟信号。来自所有上述电路的输出信号可以被传送到逻辑电路，以便产生增强的锁定检测信号。扩展锁定检测信号也可以被传送到逻辑电路。

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