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    • 1. 发明授权
    • Deep trench decoupling capacitor
    • 深沟槽去耦电容
    • US08492816B2
    • 2013-07-23
    • US12685156
    • 2010-01-11
    • James S. NakosEdmund J. SprogisAnthony K. Stamper
    • James S. NakosEdmund J. SprogisAnthony K. Stamper
    • H01L27/108H01L29/94
    • H01L28/40H01L29/66181H01L29/945
    • Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.
    • 公开了用于形成硅化深沟槽去耦电容器的解决方案。 一方面,半导体结构在硅衬底内包括沟槽电容器,所述沟槽电容器包括:延伸到硅衬底中的外沟槽; 介电衬垫层,与所述外沟槽接触; 所述掺杂多晶硅层在所述外部沟槽内形成内部沟槽; 以及在所述掺杂多晶硅层的一部分上的硅化物层,所述硅化物层将所述接触的至少一部分与所述掺杂多晶硅层的至少一部分分离; 以及具有与所述沟槽电容器邻接的下表面的接触件,所述下表面的一部分不邻接所述硅化物层。
    • 2. 发明申请
    • DEEP TRENCH DECOUPLING CAPACITOR
    • 深层解压电容器
    • US20110169131A1
    • 2011-07-14
    • US12685156
    • 2010-01-11
    • James S. NakosEdmund J. SprogisAnthony K. Stamper
    • James S. NakosEdmund J. SprogisAnthony K. Stamper
    • H01L29/94H01L21/02
    • H01L28/40H01L29/66181H01L29/945
    • Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.
    • 公开了用于形成硅化深沟槽去耦电容器的解决方案。 一方面,半导体结构在硅衬底内包括沟槽电容器,所述沟槽电容器包括:延伸到硅衬底中的外沟槽; 介电衬垫层,与所述外沟槽接触; 所述掺杂多晶硅层在所述外部沟槽内形成内部沟槽; 以及在所述掺杂多晶硅层的一部分上的硅化物层,所述硅化物层将所述接触的至少一部分与所述掺杂多晶硅层的至少一部分分离; 以及具有与所述沟槽电容器邻接的下表面的接触件,所述下表面的一部分不邻接所述硅化物层。
    • 6. 发明授权
    • Through wafer vias with dishing correction methods
    • 通过具有凹陷校正方法的晶片通孔
    • US08166651B2
    • 2012-05-01
    • US12181359
    • 2008-07-29
    • Peter J. LindgrenEdmund J. SprogisAnthony K. Stamper
    • Peter J. LindgrenEdmund J. SprogisAnthony K. Stamper
    • H01K3/10H05K3/02H05K3/10H01L29/40
    • H01L21/76898H01L21/76838H01L21/7684H01L23/522H01L2924/0002H01L2924/00
    • A method of forming a through wafer via including forming the through wafer via (TWV) into a substrate and through a first dielectric layer over the substrate; planarizing the first dielectric layer using a chemical mechanical polish before forming a second dielectric layer; forming the second dielectric layer over the substrate and the TWV; forming at least one first contact through the second dielectric layer and to the TWV; forming at least one second contact through the second dielectric layer and the first dielectric layer directly and electrically connected to another structure upon the substrate; and forming a first metal wiring layer directly over the second dielectric layer, the first metal wiring layer directly and physically contacting the at least one first contact and the at least one second contact.
    • 一种形成贯穿晶片通孔的方法,包括通过(TWV)形成贯穿晶片进入衬底并穿过衬底上的第一介电层; 在形成第二电介质层之前,使用化学机械抛光平面化第一介电层; 在所述衬底和所述TWV上形成所述第二电介质层; 通过所述第二介电层和所述TWV形成至少一个第一接触; 通过所述第二电介质层和所述第一介电层形成至少一个第二接触,并且在所述衬底上直接电连接到另一结构; 以及直接在所述第二电介质层上方形成第一金属布线层,所述第一金属布线层直接地和物理地接触所述至少一个第一触点和所述至少一个第二触点。
    • 8. 发明申请
    • Photomasks having sub-lithographic features to prevent undesired wafer patterning
    • 具有亚光刻特征以防止不期望的晶片图案化的光掩模
    • US20110177435A1
    • 2011-07-21
    • US12690312
    • 2010-01-20
    • Russell T. HerrinEdmund J. SprogisAnthony K. Stamper
    • Russell T. HerrinEdmund J. SprogisAnthony K. Stamper
    • G03F1/00
    • G03F1/42G03F1/36G03F1/38
    • A photomask that is used as a light filter in an exposure system is made of at least one layer of material comprising one or more transparent regions and one or more non-transparent regions. The difference between the transparent regions and the non-transparent regions defines the features that will be illuminated by the exposure system on a photoresist that will be exposed using the exposure system. The features comprise one or more device shapes and at least one sub-lithographic shape that will be exposed upon the photoresist. The sub-lithographic shape has an sub-lithographic shape size that is limited in such a way that the sub-lithographic shape causes a physical change only in a surface of the photoresist. Therefore, because the sub-lithographic shape is so small, it avoids forming an opening through the photoresist after the photoresist is developed and only causes a change on the surface of the photoresist.
    • 在曝光系统中用作滤光器的光掩模由包括一个或多个透明区域和一个或多个不透明区域的至少一层材料制成。 透明区域和不透明区域之间的差异限定了曝光系统将在将使用曝光系统曝光的光刻胶上照亮的特征。 这些特征包括一个或多个器件形状和将被暴露在光刻胶上的至少一个亚光刻形状。 亚光刻形状具有亚光刻形状尺寸,其受到限制,使得亚光刻形状仅在光致抗蚀剂的表面引起物理变化。 因此,由于亚光刻形状如此之小,因此避免了在光致抗蚀剂显影之后通过光致抗蚀剂形成开口,并且仅引起光致抗蚀剂表面的变化。