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1. 发明授权

US08027416B2 Structure for data communications systems 失效
标题翻译：数据通信系统的结构
公开(公告)号：US08027416B2
公开(公告)日：2011-09-27
申请号：US12043166
申请日：2008-03-06
申请人： James S. Mason , Louis C. Hsu , Phil J. Murfet , Gareth J. Nicholls
发明人： James S. Mason , Louis C. Hsu , Phil J. Murfet , Gareth J. Nicholls
IPC分类号： H04L27/08
CPC分类号： H04L25/063 , H04L25/0292
摘要： A machine-readable medium thereupon stored a design structure; the design structure includes a receiver for a data communications system. The receiver includes a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.
摘要翻译：机器可读介质存储设计结构; 该设计结构包括用于数据通信系统的接收器。接收机包括用于从数据信道接收数据信号的数据路径，数据路径包括自动增益控制（AGC）环路; 以及信号检测器，用于响应于在信道上的数据信号的检测超过阈值并且根据来自数据路径中的AGC循环的增益信息，产生指示数据信号的有效性的数据有效信号。

2. 发明申请

US20080037690A1 DATA COMMUNICATIONS SYSTEMS 失效
标题翻译：数据通信系统
公开(公告)号：US20080037690A1
公开(公告)日：2008-02-14
申请号：US11737319
申请日：2007-04-19
申请人： James S. Mason , Louis C. Hsu , Phil J. Murfet , Gareth J. Nicholls
发明人： James S. Mason , Louis C. Hsu , Phil J. Murfet , Gareth J. Nicholls
IPC分类号： H04L27/08 , H03K9/00
CPC分类号： H04L25/0292 , H04L25/063
摘要： A receiver for a data communications system comprises: a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.
摘要翻译：用于数据通信系统的接收机包括：用于从数据信道接收数据信号的数据路径，所述数据路径包括自动增益控制（AGC）环路; 以及信号检测器，用于响应于在信道上的数据信号的检测超过阈值并且根据来自数据路径中的AGC循环的增益信息，产生指示数据信号的有效性的数据有效信号。

3. 发明授权

US08027415B2 Data communications systems 失效
标题翻译：数据通信系统
公开(公告)号：US08027415B2
公开(公告)日：2011-09-27
申请号：US11737319
申请日：2007-04-19
申请人： James S. Mason , Louis C. Hsu , Phil J. Murfet , Gareth J. Nicholls
发明人： James S. Mason , Louis C. Hsu , Phil J. Murfet , Gareth J. Nicholls
IPC分类号： H04L27/08
CPC分类号： H04L25/0292 , H04L25/063
摘要： A receiver for a data communications system comprises: a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.
摘要翻译：用于数据通信系统的接收机包括：用于从数据信道接收数据信号的数据路径，所述数据路径包括自动增益控制（AGC）环路; 以及信号检测器，用于响应于在信道上的数据信号的检测超过阈值并且根据来自数据路径中的AGC循环的增益信息，产生指示数据信号的有效性的数据有效信号。

4. 发明申请

US20080146181A1 DESIGN STRUCTURE FOR DATA COMMUNICATIONS SYSTEMS 失效
标题翻译：数据通信系统的设计结构
公开(公告)号：US20080146181A1
公开(公告)日：2008-06-19
申请号：US12043166
申请日：2008-03-06
申请人： James Mason , Louis Hsu , Phil J. Murfet , Gareth J. Nicholls
发明人： James Mason , Louis Hsu , Phil J. Murfet , Gareth J. Nicholls
IPC分类号： H04B1/06
CPC分类号： H04L25/063 , H04L25/0292
摘要： A machine-readable medium thereupon stored a design structure; the design structure includes a receiver for a data communications system. The receiver includes a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.
摘要翻译：机器可读介质存储设计结构; 该设计结构包括用于数据通信系统的接收器。接收机包括用于从数据信道接收数据信号的数据路径，数据路径包括自动增益控制（AGC）环路; 以及信号检测器，用于响应于在信道上的数据信号的检测超过阈值并且根据来自数据路径中的AGC循环的增益信息，产生指示数据信号的有效性的数据有效信号。

5. 发明申请

US20080284517A1 Variable Gain Amplifier 有权
标题翻译：可变增益放大器
公开(公告)号：US20080284517A1
公开(公告)日：2008-11-20
申请号：US12130453
申请日：2008-05-30
申请人： Thomas J. Bardsley , Matthew R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Gareth J. Nicholls
发明人： Thomas J. Bardsley , Matthew R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Gareth J. Nicholls
IPC分类号： H03G3/10
CPC分类号： H03F3/45475 , H03F1/0277 , H03F3/211 , H03F3/45179 , H03F3/72 , H03F2203/45138 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03G2201/103 , H03G2201/504
摘要： A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212). The gain of the amplifier array has a range from a low gain setting with a first amplifier stage (202) enabled, through increasing gain settings as the gain of the first amplifier stage is increased from a minimum to a maximum gain, a second amplifier stage (201) can then be enabled in addition to the first amplifier stage and the gain of the second amplifier stage increased from a minimum to a maximum gain, further amplifier stages are enabled as available up to a maximum gain setting for the amplifier array. Each amplifier stage that is enabled has a decreasingly attenuated input signal and a final amplifier stage to be enabled has a full input signal (203).
摘要翻译：提供了改变放大器和放大器阵列的增益的方法。放大器阵列包括与具有增益控制装置的每个放大器级并联连接的两个或更多个放大器级（201,202）。为每个放大器级提供输入信号装置（203,204），放大器级的输入信号具有不同的幅度。提供了用于启用和禁用放大器级（216）的装置，用于对使能的放大器级的输出进行求和以获得输出信号（212）的装置。放大器阵列的增益具有从具有第一放大级（202）使能的低增益设置的范围，通过当第一放大器级的增益从最小增益增加到最大增益时增加增益设置，第二放大器级（201）除了第一放大器级以及第二放大器级的增益从最小增益增加到最大增益之外，还可以使能另外的放大器级，直至达到放大器阵列的最大增益设置。启用的每个放大器级具有递减衰减的输入信号，并且待使能的最终放大器级具有完整输入信号（203）。

6. 发明授权

US07397302B2 Variable gain amplifier 有权
标题翻译：可变增益放大器
公开(公告)号：US07397302B2
公开(公告)日：2008-07-08
申请号：US11734864
申请日：2007-04-13
申请人： Thomas J. Bardsley , Matthew R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Gareth J. Nicholls
发明人： Thomas J. Bardsley , Matthew R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Gareth J. Nicholls
IPC分类号： H03F1/14
CPC分类号： H03F3/45475 , H03F1/0277 , H03F3/211 , H03F3/45179 , H03F3/72 , H03F2203/45138 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03G2201/103 , H03G2201/504
摘要： A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212). The gain of the amplifier array has a range from a low gain setting with a first amplifier stage (202) enabled, through increasing gain settings as the gain of the first amplifier stage is increased from a minimum to a maximum gain, a second amplifier stage (201) can then be enabled in addition to the first amplifier stage and the gain of the second amplifier stage increased from a minimum to a maximum gain, further amplifier stages are enabled as available up to a maximum gain setting for the amplifier array. Each amplifier stage that is enabled has a decreasingly attenuated input signal and a final amplifier stage to be enabled has a full input signal (203).
摘要翻译：提供了改变放大器和放大器阵列的增益的方法。放大器阵列包括与具有增益控制装置的每个放大器级并联连接的两个或更多个放大器级（201,202）。为每个放大器级提供输入信号装置（203,204），放大器级的输入信号具有不同的幅度。提供了用于启用和禁用放大器级（216）的装置，用于对使能的放大器级的输出进行求和以获得输出信号（212）的装置。放大器阵列的增益具有从具有第一放大级（202）使能的低增益设置的范围，通过当第一放大器级的增益从最小增益增加到最大增益时增加增益设置，第二放大器级（201）除了第一放大器级以及第二放大器级的增益从最小增益增加到最大增益之外，还可以使能另外的放大器级，直至达到放大器阵列的最大增益设置。启用的每个放大器级具有递减衰减的输入信号，并且待使能的最终放大器级具有完整输入信号（203）。

7. 发明授权

US07250814B2 Variable gain amplifier 有权
标题翻译：可变增益放大器
公开(公告)号：US07250814B2
公开(公告)日：2007-07-31
申请号：US11096854
申请日：2005-04-01
申请人： Thomas J. Bardsley , Matthew R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Gareth J. Nicholls
发明人： Thomas J. Bardsley , Matthew R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Gareth J. Nicholls
IPC分类号： H03F1/14
CPC分类号： H03F3/45475 , H03F1/0277 , H03F3/211 , H03F3/45179 , H03F3/72 , H03F2203/45138 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03G2201/103 , H03G2201/504
摘要： A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212). The gain of the amplifier array has a range from a low gain setting with a first amplifier stage (202) enabled, through increasing gain settings as the gain of the first amplifier stage is increased from a minimum to a maximum gain, a second amplifier stage (201) can then be enabled in addition to the first amplifier stage and the gain of the second amplifier stage increased from a minimum to a maximum gain, further amplifier stages are enabled as available up to a maximum gain setting for the amplifier array. Each amplifier stage that is enabled has a decreasingly attenuated input signal and a final amplifier stage to be enabled has a full input signal (203).
摘要翻译：提供了改变放大器和放大器阵列的增益的方法。放大器阵列包括与具有增益控制装置的每个放大器级并联连接的两个或更多个放大器级（201,202）。为每个放大器级提供输入信号装置（203,204），放大器级的输入信号具有不同的幅度。提供了用于启用和禁用放大器级（216）的装置，用于对使能的放大器级的输出进行求和以获得输出信号（212）的装置。放大器阵列的增益具有从具有第一放大级（202）使能的低增益设置的范围，通过当第一放大器级的增益从最小增益增加到最大增益时增加增益设置，第二放大器级（201）除了第一放大器级以及第二放大器级的增益从最小增益增加到最大增益之外，还可以使能另外的放大器级，直至达到放大器阵列的最大增益设置。启用的每个放大器级具有递减衰减的输入信号，并且待使能的最终放大器级具有完整输入信号（203）。

8. 发明授权

US07085970B2 Fast detection of incorrect sampling in an oversampling clock and data recovery system 失效
标题翻译：在过采样时钟和数据恢复系统中快速检测不正确的采样
公开(公告)号：US07085970B2
公开(公告)日：2006-08-01
申请号：US10201868
申请日：2002-07-23
申请人： Gareth J. Nicholls , Alexander H. Ainscow , Jon D. Garlett , Bobak Modaress-Razavi , Vernon R. Norman , Martin L. Schmatz
发明人： Gareth J. Nicholls , Alexander H. Ainscow , Jon D. Garlett , Bobak Modaress-Razavi , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H03M13/00 , G11B27/00 , H04L7/00
CPC分类号： H04L7/0083 , G11B20/10009 , G11B20/14 , H03L7/091 , H03L7/095 , H03L2207/14
摘要： A method, in an oversampling clock and data recovery system, for detecting that sampling is stuck taking place at a data edge, by detecting a data edge in an early or a late region relative to a good region and incrementing a stuck early or stuck late counter; and if one counter reaching a maximum, setting a condition indicating that sampling is stuck taking place at a data edge. If a data edge is detected in the good region, or in each of an early and a late region in a single data period, the stuck counters are reset to zero. The detection of which stuck counter has reached a maximum can cause the moving of a sampling clock forward or backward, ending when a data edge occurs in a good region, or in each of an early region and a late region in a single data period.
摘要翻译：在过采样时钟和数据恢复系统中，通过检测相对于良好区域的早期或晚期区域中的数据边缘并且早期或卡滞的延迟增加来检测在数据边缘处发生采样的方法计数器; 并且如果一个计数器达到最大值，则设置指示在数据边缘发生采样的条件。如果在单个数据周期内的良好区域或早期和晚期区域的每个区域中检测到数据边缘，则卡住的计数器将重置为零。哪个卡住的计数器的检测已经达到最大值可能导致采样时钟向前或向后移动，当数据沿出现在良好区域中时，或者在单个数据周期的早期区域和晚期区域中的每一个中结束。

9. 发明申请

US20080240224A1 STRUCTURE FOR ONE-SAMPLE-PER-BIT DECISION FEEDBACK EQUALIZER (DFE) CLOCK AND DATA RECOVERY 审中-公开
标题翻译：一次性决策反馈均衡器（DFE）时钟和数据恢复的结构
公开(公告)号：US20080240224A1
公开(公告)日：2008-10-02
申请号：US12138214
申请日：2008-06-12
申请人： JUAN A. CARBALLO , Hayden C. Cranford , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
发明人： JUAN A. CARBALLO , Hayden C. Cranford , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04L27/01
CPC分类号： H04L25/03885 , H04L25/03057 , H04L2025/03356
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER) is provided. The design generally includes a receiver circuit. The receiver circuit generally includes a decision feedback equalizer (DFE) that produces one sample per bit, and means for automatically self-adjusting the DFE to enable an eye centering process by which peak energy is maintained within the receiver circuit when phase error is a minimum.
摘要翻译：一种体现在机器可读存储介质中的设计结构，用于设计，制造和/或测试利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的设计提供接收机并降低误码率（BER）。该设计通常包括接收器电路。接收器电路通常包括每位产生一个采样的判决反馈均衡器（DFE），以及用于自动自调整DFE的装置，以便当相位误差最小时能够在接收器电路内保持峰值能量的眼睛对中过程。

10. 发明授权

US07809054B2 One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery 失效
标题翻译：单采样每位决策反馈均衡器（DFE）时钟和数据恢复
公开(公告)号：US07809054B2
公开(公告)日：2010-10-05
申请号：US11405997
申请日：2006-04-18
申请人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
发明人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03063
摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.
摘要翻译：公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。输入电压被转换为电流并连接到电流求和节点。由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。另外，总和电流被积分并转换成电压。采样器用于基于所得到的电压进行位决定。采样后，积分器在分析下一位之前被复位。通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。

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