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1. 发明授权

US5546588A Method and apparatus for preventing a data processing system from entering a non-recoverable state 失效
标题翻译：防止数据处理系统进入不可恢复状态的方法和装置
公开(公告)号：US5546588A
公开(公告)日：1996-08-13
申请号：US350396
申请日：1994-12-05
申请人： Vincent B. Deems , Gregory A. Racino , James R. Feddeler , Victor E. Shiff
发明人： Vincent B. Deems , Gregory A. Racino , James R. Feddeler , Victor E. Shiff
IPC分类号： G06F9/30 , G06F9/00
CPC分类号： G06F9/30083
摘要： A method and apparatus for preventing a data processing system (10) from entering a non-recoverable state. In one form, the present invention uses a pin (40) to indicate whether or not the execution of a non-recoverable instruction is legal. If the pin indicates that the execution of the instruction is legal, then the instruction is executed and the data processing system (10) is placed into a state that requires an external stimulus in order to recover. If the pin indicates that the execution of the instruction is illegal, then the instruction is not permitted to place the data processing system (10) into a state that requires an external stimulus in order to recover. Instead, an internal recovery mechanism is provided which returns the data processing system (10) to normal processing.
摘要翻译：一种用于防止数据处理系统（10）进入不可恢复状态的方法和装置。在一种形式中，本发明使用销（40）来指示不可恢复指令的执行是否合法。如果引脚指示指令的执行是合法的，则执行指令，并且数据处理系统（10）被置于需要外部刺激以恢复的状态。如果引脚指示执行指令是非法的，则不允许指令将数据处理系统（10）置于需要外部刺激的状态以便恢复。而是提供一种将数据处理系统（10）返回到正常处理的内部恢复机制。

2. 发明授权

US5323066A Method and apparatus for performing power on reset initialization in a data processing system 失效
标题翻译：在数据处理系统中对重置初始化进行电力的方法和装置
公开(公告)号：US5323066A
公开(公告)日：1994-06-21
申请号：US891066
申请日：1992-06-01
申请人： James R. Feddeler , Gregory A. Racino
发明人： James R. Feddeler , Gregory A. Racino
IPC分类号： G06F1/24 , H03K17/22 , H03K3/01
CPC分类号： H03K17/223 , G06F1/24
摘要： A method and apparatus for performing power on reset initialization in a data processing system (40). In one form, the present invention uses a circuit (71) to ensure that a node (65) always power up to the correct logic level. This node (65) can then be used to initialize a latch (83) so that the latch (83) always drives a predetermined logic level at its data output when the latch (83) powers up. The data output of latch (83) is a Power On Reset signal which is asserted during power on reset initialization and which is negated when power on reset initialization is completed.
摘要翻译：一种用于在数据处理系统（40）中对复位初始化进行电力的方法和装置。在一种形式中，本发明使用电路（71）来确保节点（65）总是上电到正确的逻辑电平。然后可以使用该节点（65）来初始化锁存器（83），使得当锁存器（83）上电时，锁存器（83）总是在其数据输出处驱动预定的逻辑电平。锁存器（83）的数据输出是上电复位信号，其在上电复位初始化期间被置位，并且在上电复位初始化完成时被否定。

3. 发明授权

US5559981A Pseudo static mask option register and method therefor 失效
标题翻译：伪静态掩码选项寄存器及其方法
公开(公告)号：US5559981A
公开(公告)日：1996-09-24
申请号：US194900
申请日：1994-02-14
申请人： Gregory A. Racino , Jeffrey R. Jorvig
发明人： Gregory A. Racino , Jeffrey R. Jorvig
IPC分类号： G11C16/20 , G06F12/00
CPC分类号： G11C16/20
摘要： A pseudo-static mask option register (50) combines features of both a continuous refresh design and a static latched mask option register design. Pseudo-static mask option register (50) removes a mask option function from a main user memory (48) such that the functionality of the mask option register (50) is not limited by a plurality of electrical characteristics of the main use memory (48). When using the pseudo-static mask option register (50), a memory state of each memory bit (64, 66, 68) is read at any time. Additionally, a portion of the memory bits (64, 66, 68) is periodically refreshed such that pseudo-static mask option register (50) maintains an integrity of a value stored therein while minimizing power consumption. Pseudo-static mask option register (50) also has a non-volatile output state to allow emulation of mask options which are vulnerable to electrical disturbances.
摘要翻译：伪静态掩码选项寄存器（50）组合了连续刷新设计和静态锁存掩码选项寄存器设计的特征。伪静态掩码选项寄存器（50）从主用户存储器（48）中去除掩码选项功能，使得掩码选项寄存器（50）的功能不受主要使用存储器（48）的多个电特性的限制）。当使用伪静态掩码选项寄存器（50）时，随时读取每个存储器位（64,66,68）的存储器状态。此外，存储器位（64,66,68）的一部分被周期性刷新，使得伪静态掩模选项寄存器（50）保持其中存储的值的完整性，同时最小化功耗。伪静态掩模选项寄存器（50）还具有非易失性输出状态，以允许仿真易受电扰动的掩模选项。

4. 发明授权

US5675469A Integrated circuit with electrostatic discharge (ESD) protection and ESD protection circuit 失效
标题翻译：具有静电放电（ESD）保护和ESD保护电路的集成电路
公开(公告)号：US5675469A
公开(公告)日：1997-10-07
申请号：US501530
申请日：1995-07-12
申请人： Gregory A. Racino , Kenneth Obuszewski
发明人： Gregory A. Racino , Kenneth Obuszewski
IPC分类号： H01L27/02 , H02H9/04
CPC分类号： H01L27/0262 , H01L27/0251
摘要： An integrated circuit (20) includes an ESD protection circuit (50) to protect it from excessive electrostatic discharge voltages. The ESD protection circuit (50) includes a diode (51) in series with a silicon controlled rectifier (SCR) (60) connected between an input signal line (42) and a power supply voltage terminal. Unlike conventional protection circuits, the ESD protection circuit (50) allows the voltage on the input signal line (42) to extend well beyond positive and negative power supply potentials, and only becomes conductive to discharge voltages which are outside of this extended range.
摘要翻译：集成电路（20）包括ESD保护电路（50），以防止其过度的静电放电电压。 ESD保护电路（50）包括与连接在输入信号线（42）和电源电压端子之间的可控硅整流器（SCR）串联的二极管（51）。与常规保护电路不同，ESD保护电路（50）允许输入信号线（42）上的电压远远超过正电源电压和负电源电位，并且仅对超出该扩展范围的放电电压变为导通。

5. 发明授权

US5199032A Microcontroller having an EPROM with a low voltage program inhibit circuit 失效
标题翻译：具有低电压编程禁止电路的EPROM的微控制器
公开(公告)号：US5199032A
公开(公告)日：1993-03-30
申请号：US576864
申请日：1990-09-04
申请人： Robert W. Sparks , Gregory A. Racino , Brian R. Gardner
发明人： Robert W. Sparks , Gregory A. Racino , Brian R. Gardner
IPC分类号： G06F11/00 , G11C16/10 , G11C16/22 , G11C16/30
CPC分类号： G11C16/30 , G06F11/004 , G11C16/10 , G11C16/225 , G06F11/0754
摘要： A microcontroller is provided having an on-chip electrically erasable programmable read-only-memory (EEPROM), which is user programmable via a programming register. The microcontroller includes a low voltage program inhibit (LVPI) circuit which is combined with the existing EEPROM design. By integrating the LVPI circuit into the EEPROM, the EEPROM may be protected without disabling the entire data processing system. If the supply voltage (V.sub.DD) falls below a predetermined voltage level, the LVPI circuit inhibits the use of the EEPROM programming register, thereby preventing the CPU from programming or erasing the EEPROM. A comparator in the LVPI circuit compares a precision reference voltage to a voltage divided off of the power supply (V.sub.DD), and provides a output signal to the EEPROM programming register. During normal operation, the comparator output signal is a logic low, which enables the user to program or erase the EEPROM, via the programming register. When the supply voltage is below the predetermined safe level, the comparator output signal is a logic high signal, which sets a control bit in the programming register. When set, the control bit clears the remaining bits in the programming register, thereby disabling a charge pump, and preventing any further EEPROM programming.
摘要翻译：提供具有片上电可擦除可编程只读存储器（EEPROM）的微控制器，其可由用户通过编程寄存器编程。微控制器包括与现有EEPROM设计相结合的低电压程序禁止（LVPI）电路。通过将LVPI电路集成到EEPROM中，可以保护EEPROM而不使整个数据处理系统无效。如果电源电压（VDD）低于预定电压电平，则LVPI电路禁止使用EEPROM编程寄存器，从而防止CPU编程或擦除EEPROM。 LVPI电路中的比较器将精密参考电压与分压掉电源（VDD）的电压进行比较，并将输出信号提供给EEPROM编程寄存器。正常工作期间，比较器输出信号为逻辑低电平，使用户可以通过编程寄存器对EEPROM进行编程或擦除。当电源电压低于预定安全电平时，比较器输出信号为逻辑高电平信号，用于设置编程寄存器中的控制位。置位时，控制位清除编程寄存器中的剩余位，从而禁用电荷泵，并防止进行任何进一步的EEPROM编程。

6. 发明授权

US5390317A Technique to support progressively programmable nonvolatile memory 失效
标题翻译：技术支持逐步编程的非易失性存储器
公开(公告)号：US5390317A
公开(公告)日：1995-02-14
申请号：US210409
申请日：1994-03-18
申请人： Donald G. Weiss , Laura M. Dobbs , James S. Thomas , Gregory A. Racino
发明人： Donald G. Weiss , Laura M. Dobbs , James S. Thomas , Gregory A. Racino
IPC分类号： G11C17/00 , G06F12/14 , G11C16/08 , G06F12/00 , G06F12/16
CPC分类号： G06F12/1433 , G11C16/08
摘要： A nonvolatile memory (28) in a data processor (10) is capable of being progressively programmed and/or accessed in a user determined number of sections. A user can program and/or access what appears to the user to be reprogrammable nonvolatile memory (28) at a same address when in actuality the user is programming and accessing sequential sections of nonvolatile memory (28). Nonvolatile information stored in nonvolatile control bits (20) is used to control which section of the nonvolatile memory is connected to a communication bus and is thus accessible to the user. When the user desires to write and/or access a new section of nonvolatile memory (28), either the user directly asserts one of the nonvolatile control bits (20) using software, or the nonvolatile control (24) asserts one of the nonvolatile control bits (20) using hardware.
摘要翻译：数据处理器（10）中的非易失性存储器（28）能够以用户确定的部分数量逐渐编程和/或访问。当实际上用户正在编程和访问非易失性存储器（28）的顺序部分时，用户可以编程和/或访问在同一地址处对用户进行重新编程的非易失性存储器（28）的显示。存储在非易失性控制位（20）中的非易失性信息用于控制非易失性存储器的哪一部分连接到通信总线，并且由此可被用户访问。当用户期望写入和/或访问非易失性存储器（28）的新部分时，用户使用软件直接断言其中一个非易失性控制位（20），或者非易失性控制（24）断言非易失性控制位（20）使用硬件。

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