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1. 发明授权

US06857033B1 I/O node for a computer system including an integrated graphics engine and an integrated I/O hub 有权
标题翻译：用于包括集成图形引擎和集成I / O集线器的计算机系统的I / O节点
公开(公告)号：US06857033B1
公开(公告)日：2005-02-15
申请号：US10034967
申请日：2001-12-27
申请人： Dale E. Gulick , Larry D. Hewitt , James Mergard
发明人： Dale E. Gulick , Larry D. Hewitt , James Mergard
IPC分类号： G06F3/14 , G06F13/38 , G06F13/42
CPC分类号： G06F13/4265 , G06F3/14
摘要： An I/O node for a computer system including an integrated graphics engine and integrated I/O hub. An input/output node that is implemented on an integrated circuit chip includes a transceiver unit, a graphics engine and an I/O hub. The transceiver unit may receive and transmit packets on a point-to-point link of a packet interface. The graphics engine may be coupled to receive graphics packets received by the transceiver unit and may render digital image information in response to receiving the graphics packets. The I/O hub may be coupled to receive I/O packets corresponding to packets received by the transceiver unit and may initiate bus cycles corresponding to the I/O packets upon a peripheral bus. The packet interface link may be a point-to-point HyperTransport™ link including a first and second set of uni-directional wires which may convey control and data packets over the same wires.
摘要翻译：用于计算机系统的I / O节点，包括集成图形引擎和集成I / O集线器。在集成电路芯片上实现的输入/输出节点包括收发器单元，图形引擎和I / O集线器。收发器单元可以在分组接口的点对点链路上接收和发送分组。图形引擎可以被耦合以接收由收发器单元接收的图形分组，并且可以响应于接收到图形分组而呈现数字图像信息。 I / O集线器可以被耦合以接收对应于由收发器单元接收的分组的I / O分组，并且可以在外围总线上启动对应于I / O分组的总线周期。分组接口链路可以是包括可以通过相同线路传送控制和数据分组的第一和第二组单向导线的点对点HyperTransport TM链路。

2. 发明授权

US06791554B1 I/O node for a computer system including an integrated graphics engine 有权
标题翻译：包含集成显卡引擎的计算机系统的I / O节点
公开(公告)号：US06791554B1
公开(公告)日：2004-09-14
申请号：US10034560
申请日：2001-12-27
申请人： James Mergard , Dale E. Gulick , Larry D. Hewitt
发明人： James Mergard , Dale E. Gulick , Larry D. Hewitt
IPC分类号： G06F1576
CPC分类号： G06T1/20
摘要： An I/O node for a computer system including an integrated graphics engine. An input/output node is implemented upon an integrated circuit chip. The I/O node includes a first transceiver unit, a second transceiver unit, a packet tunnel, a graphics engine and a graphics interface. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus and the second transceiver unit may receive and transmit packet transactions on a second link. The packet tunnel may convey selected packet transactions between the first and the second transceiver unit. The graphics engine may receive graphics packet transactions from the first transceiver unit and may render digital image information in response to receiving the graphics transactions. The graphics interface may receive additional graphics packet transactions from the first transceiver unit and may translate the additional graphics packet transactions into transactions suitable for transmission upon a graphics bus.
摘要翻译：用于包括集成图形引擎的计算机系统的I / O节点。输入/输出节点在集成电路芯片上实现。 I / O节点包括第一收发器单元，第二收发器单元，分组隧道，图形引擎和图形接口。第一收发器单元可以在分组总线的第一链路上接收和发送分组交易，并且第二收发器单元可以在第二链路上接收和发送分组交易。分组隧道可以在第一和第二收发器单元之间传送所选择的分组事务。图形引擎可以从第一收发器单元接收图形分组交易，并且可以响应于接收到图形交易而呈现数字图像信息。图形接口可以从第一收发器单元接收额外的图形分组事务，并且可以将附加的图形分组事务转换成适于在图形总线上传输的事务。

3. 发明授权

US5881248A System and method for optimizing system bus bandwidth in an embedded communication system 失效
标题翻译：嵌入式通信系统中优化系统总线带宽的系统和方法
公开(公告)号：US5881248A
公开(公告)日：1999-03-09
申请号：US812218
申请日：1997-03-06
申请人： James Mergard
发明人： James Mergard
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A communication system which includes more efficient bus utilization for higher data throughput. The communication system includes various logic devices connected to a system bus. The communication system intelligently utilizes unused system bus bandwidth for improved performance. The communication system includes a receive buffer, a memory, a central processing unit (CPU), a direct memory access (DMA) controller, and a bus arbiter each preferably coupled to the system bus. The buffer is operable to generate a low priority DMA transfer request when any amount of data is stored in the buffer. The buffer is also operable to generate a high priority DMA transfer request when a certain threshold or amount of data is stored in the buffer, i.e., when a certain "water-level" has been reached. When the buffer generates the low priority DMA request, the DMA controller and/or bus determine if the system bus is otherwise not being utilized, e.g., if the CPU is currently operating out of its cache system and no other devices have requested or are using the bus. If so, the DMA transfers are allowed to proceed. The high priority DMA transfer request operates normally, guaranteeing access to the system bus to avoid FIFO overruns.
摘要翻译：一种通信系统，其包括更高效的总线利用率以实现更高的数据吞吐通信系统包括连接到系统总线的各种逻辑设备。通信系统智能地利用未使用的系统总线带宽来提高性能。通信系统包括接收缓冲器，存储器，中央处理单元（CPU），直接存储器访问（DMA）控制器和总线仲裁器，每个优选地耦合到系统总线。当缓冲器中存储任何数量的数据时，缓冲器可操作以产生低优先级的DMA传输请求。当某个阈值或数据量存储在缓冲器中时，即当达到某个“水位”时，该缓冲器还可以用于产生高优先级的DMA传输请求。当缓冲器产生低优先级的DMA请求时，DMA控制器和/或总线确定系统总线是否被不被利用，例如，如果CPU当前正在其高速缓存系统中运行，并且没有其他设备已经请求或正在使用公交车。如果是这样，DMA传输被允许继续。高优先级DMA传输请求正常运行，保证访问系统总线以避免FIFO溢出。

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