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1. 发明申请

US20080126714A1 Data transfer coherency device and methods thereof 有权
标题翻译：数据传输一致性设备及其方法
公开(公告)号：US20080126714A1
公开(公告)日：2008-05-29
申请号：US11510369
申请日：2006-08-25
申请人： James M. Sibigtroth , Michael W. Rhoades , Michael C. Wood , George E. Baker
发明人： James M. Sibigtroth , Michael W. Rhoades , Michael C. Wood , George E. Baker
IPC分类号： G06F13/00
CPC分类号： G06F13/4221
摘要： Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.
摘要翻译：公开了用于执行相干访问请求的方法和设备。所述方法包括接收与第一写入或读取请求相关联的第一地址。在写入操作期间，如果第一地址与相干访问寄存器相关联，则要写入的数据被存储在连接到多个相干数据访问寄存器的数据锁存器处。接收与第二写请求相关联的第二地址和第二数据。如果第二地址与第一地址匹配，则第二数据和锁存的第一数据被写入相干访问寄存器。通过锁存第一数据并同时写入锁存的第一数据和第二数据，维持写入数据的整体一致性。

2. 发明授权

US08015329B2 Data transfer coherency device and methods thereof 有权
标题翻译：数据传输一致性设备及其方法
公开(公告)号：US08015329B2
公开(公告)日：2011-09-06
申请号：US12776281
申请日：2010-05-07
申请人： James M. Sibigtroth , Michael W. Rhoades , Michael C. Wood , George E. Baker
发明人： James M. Sibigtroth , Michael W. Rhoades , Michael C. Wood , George E. Baker
IPC分类号： G06F13/00 , G06F3/00 , G06F13/14
CPC分类号： G06F13/4221
摘要： Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.
摘要翻译：公开了用于执行相干访问请求的方法和设备。所述方法包括接收与第一写入或读取请求相关联的第一地址。在写入操作期间，如果第一地址与相干访问寄存器相关联，则要写入的数据被存储在连接到多个相干数据访问寄存器的数据锁存器处。接收与第二写请求相关联的第二地址和第二数据。如果第二地址与第一地址匹配，则第二数据和锁存的第一数据被写入相干访问寄存器。通过锁存第一数据并同时写入锁存的第一数据和第二数据，维持写入数据的整体一致性。

3. 发明授权

US07743184B2 Coherent access register data transfer device and methods thereof 有权
标题翻译：相干访问寄存器数据传送装置及其方法
公开(公告)号：US07743184B2
公开(公告)日：2010-06-22
申请号：US11510369
申请日：2006-08-25
申请人： James M. Sibigtroth , Michael W. Rhoades , Michael C. Wood , George E. Baker
发明人： James M. Sibigtroth , Michael W. Rhoades , Michael C. Wood , George E. Baker
IPC分类号： G06F13/00 , G06F3/00 , G06F13/14 , G06F13/28
CPC分类号： G06F13/4221
摘要： Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.
摘要翻译：公开了用于执行相干访问请求的方法和设备。所述方法包括接收与第一写入或读取请求相关联的第一地址。在写入操作期间，如果第一地址与相干访问寄存器相关联，则要写入的数据被存储在连接到多个相干数据访问寄存器的数据锁存器处。接收与第二写请求相关联的第二地址和第二数据。如果第二地址与第一地址匹配，则第二数据和锁存的第一数据被写入相干访问寄存器。通过锁存第一数据并同时写入锁存的第一数据和第二数据，维持写入数据的整体一致性。

4. 发明申请

US20100223414A1 DATA TRANSFER COHERENCY DEVICE AND METHODS THEREOF 有权
标题翻译：数据传输相邻设备及其方法
公开(公告)号：US20100223414A1
公开(公告)日：2010-09-02
申请号：US12776281
申请日：2010-05-07
申请人： James M. Sibigtroth , Michael W. Rhoades , Michael C. Wood , George E. Baker
发明人： James M. Sibigtroth , Michael W. Rhoades , Michael C. Wood , George E. Baker
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/4221
摘要： Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.
摘要翻译：公开了用于执行相干访问请求的方法和设备。所述方法包括接收与第一写入或读取请求相关联的第一地址。在写入操作期间，如果第一地址与相干访问寄存器相关联，则要写入的数据被存储在连接到多个相干数据访问寄存器的数据锁存器处。接收与第二写请求相关联的第二地址和第二数据。如果第二地址与第一地址匹配，则第二数据和锁存的第一数据被写入相干访问寄存器。通过锁存第一数据并同时写入锁存的第一数据和第二数据，维持写入数据的整体一致性。

5. 发明授权

US06823224B2 Data processing system having an on-chip background debug system and method therefor 有权
标题翻译：具有片上后台调试系统的数据处理系统及其方法
公开(公告)号：US06823224B2
公开(公告)日：2004-11-23
申请号：US09788816
申请日：2001-02-21
申请人： Michael C. Wood , George E. Baker , James M. Sibigtroth
发明人： Michael C. Wood , George E. Baker , James M. Sibigtroth
IPC分类号： H02H305
CPC分类号： G06F11/348 , Y02D10/34
摘要： Embodiments of the present invention relate to a mechanism to prevent the oscillator from being stopped when a host development system is coupled to the background debug communications interface and the background debug mode has been enabled. This allows background debugging operations to continue when the target data processing system is in a low power mode. Other embodiments relate to a mechanism for allowing a host development system to request a synchronization timing pulse from a target data processing system so the correct clock speed can be determined for background communications. Alternate embodiments relate to a data processing system having a system clock unit and a background debug system where the background debug system includes a background debug clock unit, separate from the system clock unit, and an enable control. When the enable control is asserted, the background debug clock unit is enabled, independent of the system clock unit.
摘要翻译：本发明的实施例涉及当主机显影系统耦合到后台调试通信接口并且背景调试模式已被使能时防止振荡器停止的机制。当目标数据处理系统处于低功耗模式时，这样可以使后台调试操作继续进行。其他实施例涉及允许主机开发系统从目标数据处理系统请求同步定时脉冲的机制，从而可以为后台通信确定正确的时钟速度。替代实施例涉及具有系统时钟单元和后台调试系统的数据处理系统，其中后台调试系统包括与系统时钟单元分离的后台调试时钟单元和启用控制。当使能控制被置位时，后台调试时钟单元被使能，与系统时钟单元无关。

6. 发明授权

US5251304A Integrated circuit microcontroller with on-chip memory and external bus interface and programmable mechanism for securing the contents of on-chip memory 失效
标题翻译：具有片上存储器和外部总线接口的集成电路微控制器以及用于保护片上存储器内容的可编程机构
公开(公告)号：US5251304A
公开(公告)日：1993-10-05
申请号：US589246
申请日：1990-09-28
申请人： James M. Sibigtroth , Michael W. Rhoades , George G. Grimmer, Jr. , Susan W. Longwell
发明人： James M. Sibigtroth , Michael W. Rhoades , George G. Grimmer, Jr. , Susan W. Longwell
IPC分类号： G06F12/14 , G06F15/78 , G06F21/02 , G06F21/24 , G06F12/00
CPC分类号： G06F15/7842 , G06F12/1433
摘要： A data processor with memory within a single integrated circuit package provides a programmable "secure mode" of operation to selectively restrict access and protect information stored in its memory. The secure mode of operation is included in addition to a "single chip mode" wherein the data processor accesses both data and instructions strictly from within the single integrated circuit package. An "expanded mode" of operation also exists wherein the data processor may access either internal or external memory for both instructions and data. The secure mode of operation restricts accesses of instructions to memory contained within the single integrated circuit while allowing data accesses to memory either internal or external to the integrated circuit. The secure mode is accomplished by selectively isolating internal data/instruction bus transfer activity from an external data/instruction bus.
摘要翻译：具有单个集成电路封装内的存储器的数据处理器提供可编程的“安全模式”操作，以选择性地限制访问和保护存储在其存储器中的信息。除了单芯片模式之外，还包括安全操作模式，其中数据处理器严格地从单个集成电路封装内访问数据和指令。还存在“扩展模式”，其中数据处理器可以访问用于指令和数据的内部或外部存储器。安全操作模式限制对包含在单个集成电路内的存储器的指令的访问，同时允许对集成电路的内部或外部的存储器的数据访问。通过从外部数据/指令总线选择性地隔离内部数据/指令总线传输活动来实现安全模式。

7. 发明申请

US20080095142A1 METHOD AND APPARATUS FOR UPDATING A COUNT VALUE 审中-公开
标题翻译：更新计数值的方法和装置
公开(公告)号：US20080095142A1
公开(公告)日：2008-04-24
申请号：US11550558
申请日：2006-10-18
申请人： James M. Sibigtroth , Michael C. Wood
发明人： James M. Sibigtroth , Michael C. Wood
IPC分类号： H04J3/24
CPC分类号： H04L9/0891 , G07C9/00182 , G07C2009/00793 , G07C2209/06
摘要： A method and apparatus for updating a count value is provided. The count value includes a first portion stored in a non-volatile memory and a second portion stored in a volatile memory. The second portion of the count value is updated upon elapse of a period of time. The first portion of the count value is updated if the second portion of the count value overflowed and a use indicator corresponding to the first portion of the count value is set. The first portion of the count value is also updated if a power on reset event is detected and a use indicator corresponding to the first portion of the count value is set.
摘要翻译：提供了一种用于更新计数值的方法和装置。计数值包括存储在非易失性存储器中的第一部分和存储在易失性存储器中的第二部分。计数值的第二部分在经过一段时间后更新。如果计数值的第二部分溢出并且设置了与计数值的第一部分对应的使用指示符，则更新计数值的第一部分。如果检测到电源复位事件并且设置与计数值的第一部分相对应的使用指示符，则计数值的第一部分也被更新。

8. 发明授权

US06009012A Microcontroller having a non-volatile memory and a method for selecting an operational mode 失效
标题翻译：具有非易失性存储器的微控制器和用于选择操作模式的方法
公开(公告)号：US06009012A
公开(公告)日：1999-12-28
申请号：US89719
申请日：1998-06-03
申请人： James M. Sibigtroth , Michael C. Wood , Linda R. Nuckolls , Daniel Mark Thompson
发明人： James M. Sibigtroth , Michael C. Wood , Linda R. Nuckolls , Daniel Mark Thompson
IPC分类号： G11C16/10 , G11C16/20 , G11C29/52 , G11C16/04
CPC分类号： G11C16/102 , G11C16/20 , G11C29/52
摘要： A method for automatically detecting a programmed status of a non-volatile memory and selecting one of multiple operational modes based on that status. In one embodiment a non-volatile memory (102) has a normal and an access restricted operational mode. The memory is placed in the access restricted operational mode once it is programmed in order to prevent unauthorized access to the programmed data. A detection logic (226) determines whether the non-volatile memory is in a non-programmed state. Based on this detection it is determined whether the non-volatile memory is to be placed in a normal or an access restricted operational mode. The invention relates also to determining an operational mode of the microcontroller which can advantageously be incorporated into an assembled electronic device.
摘要翻译：一种用于自动检测非易失性存储器的编程状态并基于该状态选择多种操作模式之一的方法。在一个实施例中，非易失性存储器（102）具有正常和访问受限操作模式。一旦编程存储器就被置于访问受限操作模式中，以防止未经授权的访问编程数据。检测逻辑（226）确定非易失性存储器是否处于非编程状态。基于该检测，确定非易失性存储器是否被放置在正常或访问受限的操作模式中。本发明还涉及确定微控制器的操作模式，其可以有利地结合到组装的电子设备中。

9. 发明申请

US20080098218A1 SECURE COMMUNICATION PROTOCOL AND METHOD THEREFOR 审中-公开
标题翻译：安全通信协议及其方法
公开(公告)号：US20080098218A1
公开(公告)日：2008-04-24
申请号：US11550518
申请日：2006-10-18
申请人： James M. Sibigtroth , Michael C. Wood
发明人： James M. Sibigtroth , Michael C. Wood
IPC分类号： H04L9/00
CPC分类号： H04L63/0428 , H04L9/3242 , H04L63/123 , H04L2209/20 , H04L2209/80
摘要： A method is provided for secure communication between a transmitter and a receiver. The transmitter comprises a non-volatile memory for storing a first portion of a count value, where the count value is updated after an elapse of a period of time. The transmitter comprises a volatile memory for storing a second portion of the count value. In response to receipt of a transmit request, the transmitter sets a use indicator corresponding to the first portion of the count value. Upon elapse of the period of time, the second portion of the count value is updated. The first portion of the count value is updated if the second portion of the count value overflows and if the use indicator corresponding to the first portion set. A message authentication code is generated based on at least the count value. A message transmitted to the receiver comprises at least the message authentication code.
摘要翻译：提供了一种用于发射机和接收机之间的安全通信的方法。发射机包括用于存储计数值的第一部分的非易失性存储器，其中计数值在经过一段时间后被更新。发射机包括用于存储计数值的第二部分的易失性存储器。响应于接收到发送请求，发射机设置对应于计数值的第一部分的使用指示符。经过一段时间后，计数值的第二部分被更新。如果计数值的第二部分溢出并且与第一部分相对应的使用指示符，则更新计数值的第一部分。至少基于计数值生成消息认证码。发送到接收器的消息至少包括消息认证码。

10. 发明授权

US06760864B2 Data processing system with on-chip FIFO for storing debug information and method therefor 有权
标题翻译：具有片内FIFO的数据处理系统，用于存储调试信息及其方法
公开(公告)号：US06760864B2
公开(公告)日：2004-07-06
申请号：US09788815
申请日：2001-02-21
申请人： Michael C. Wood , Jay A. Hartvigsen , James M. Sibigtroth
发明人： Michael C. Wood , Jay A. Hartvigsen , James M. Sibigtroth
IPC分类号： G06F1100
CPC分类号： G06F11/364
摘要： A debug module (20) is provided which allows a developer to capture three types of debug information. The three types of debug information are: change-of-flow addresses, CPU data, and current instruction addresses. The debug information is captured in an on-chip debug FIFO memory (30) during program development. The debug information is provided to an external host via a serial communication interface (14) for post-processing and analysis. Storing and retrieving program information in this way is useful in microcontrollers that do not provide external access to address and data bus signals.
摘要翻译：提供了一种调试模块（20），其允许开发者捕获三种类型的调试信息。三种调试信息有：流程改变地址，CPU数据和当前指令地址。在程序开发期间，调试信息被捕获在片上调试FIFO存储器（30）中。调试信息经由用于后处理和分析的串行通信接口（14）提供给外部主机。以这种方式存储和检索程序信息对于不提供对地址和数据总线信号的外部访问的微控制器很有用。

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