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    • 1. 发明授权
    • Privilege promotion based on check of previous privilege level
    • 基于先前特权级别检查的特权推广
    • US07680999B1
    • 2010-03-16
    • US09499720
    • 2000-02-08
    • Dale C. MorrisJames M. Hull
    • Dale C. MorrisJames M. Hull
    • G06F12/00G06F12/14
    • G06F9/468G06F9/30076
    • A secure promotion mechanism promotes a current privilege level of a processor in a computer system. The current privilege level controls application instruction execution in the computer system by controlling accessibility to system resources. An operating system performs a privilege promotion instruction, which is stored in a first page of memory not writeable by an application instructions at a first privilege level. The privilege promotion instruction reads a stored previous privilege level state, compares the read previous privilege level state to the current privilege level, and if the previous privilege level state is equal to or less privileged than the current privilege level, promotes the current privilege level to a second privilege level which is higher than the first privilege level.
    • 安全促销机制促进计算机系统中处理器的当前特权级别。 当前的权限级别通过控制系统资源的可访问性来控制计算机系统中的应用程序指令执行。 操作系统执行特权提升指令,该指令被存储在不能由第一特权级别的应用指令写入的存储器的第一页中。 特权提升指令读取存储的先前的权限级别状态,将读取的先前权限级别状态与当前权限级别进行比较,并且如果先前的权限级别状态等于或低于当前权限级别的权限,则将当前权限级别提升到 第二个权限级别高于第一个权限级别。
    • 2. 发明授权
    • System and method for adding an instruction to an instruction set architecture
    • 用于向指令集架构添加指令的系统和方法
    • US07143270B1
    • 2006-11-28
    • US10769203
    • 2004-01-30
    • Kevin W. RuddAllan D. KniesDale C. MorrisJames M. Hull
    • Kevin W. RuddAllan D. KniesDale C. MorrisJames M. Hull
    • G06F9/44
    • G06F9/30181G06F9/30072G06F9/30174
    • A processor comprising a feature indicator associated with at least one of a first sequence of one or more instructions, a first register, a second register, and an execution core is provided. The execution core is configured to execute a second instruction to cause the first register to be set to a first value using the feature indicator and to cause the second register to be set to a second value using the feature indicator. The execution core is configured to execute the first sequence of one or more instructions to cause a function to be performed in response to the first value in the first register indicating a true condition, and the execution core is configured to execute a second sequence of one or more instructions to cause the function to be performed in response to the second value in the second register indicating the true condition.
    • 提供了一种包括与一个或多个指令的第一序列,第一寄存器,第二寄存器和执行核心中的至少一个相关联的特征指示符的处理器。 执行核心被配置为执行第二指令,以使用特征指示器将第一寄存器设置为第一值,并且使用特征指示器将第二寄存器设置为第二值。 执行核心被配置为执行一个或多个指令的第一序列,以使得响应于第一寄存器中指示真实条件的第一值来执行功能,并且执行核心被配置为执行一个第二序列 或更多的指令,以响应于指示真实条件的第二寄存器中的第二值来执行功能。
    • 4. 发明授权
    • Method and apparatus for performing integer multiply operations using primitive multi-media operations that operate on smaller operands
    • 使用对较小操作数进行操作的原始多媒体操作来执行整数乘法运算的方法和装置
    • US06813627B2
    • 2004-11-02
    • US09920250
    • 2001-07-31
    • James M. HullDale C. Morris
    • James M. HullDale C. Morris
    • G06F752
    • G06F7/5324G06F2207/3828
    • Integer multiply operations using data stored in an integer register file are performed using multi-media primitive instructions that operate on smaller operands. The present invention performs a multiply operation on a 32-bit or 64-bit value by performing multiply operations on a series of smaller operands to form partial products, and adding the partial products together. Data manipulation instructions are used to reposition 16-bit segments of the 32-bit operands into positions that allow the multi-media parallel multiply instructions to compute partial products, and the partial products are then added together to form the result. In every embodiment, the present invention achieves better latencies than the prior art method of performing integer multiply operations provided by the IA-64 architecture.
    • 使用在较小的操作数上操作的多媒体原语指令来执行使用存储在整数寄存器文件中的数据的整数乘法运算。 本发明通过对一系列较小的操作数执行乘法运算来形成部分乘积,并且将部分乘积相加在一起,对32位或64位值进行乘法运算。 数据操作指令用于将32位操作数的16位段重新定位到允许多媒体并行乘法指令计算部分乘积的位置,然后将部分乘积相加在一起形成结果。 在每个实施例中,本发明实现了比由IA-64架构提供的执行整数乘法运算的现有技术方法更好的延迟。
    • 5. 发明授权
    • Computer workload migration using processor pooling
    • 使用处理器池的计算机工作负载迁移
    • US08505020B2
    • 2013-08-06
    • US12870835
    • 2010-08-29
    • Christophe de DinechinDale C. MorrisPatrick KnebelRuss W. Herrell
    • Christophe de DinechinDale C. MorrisPatrick KnebelRuss W. Herrell
    • G06F9/46G06F15/173G06F1/00G06F11/00
    • G06F9/5088
    • An event calling for a migration of a workload from a source processor set of processing units to a target processor set of processing units is detected. Processes of the workload are allocated to a second processor set of processing units so that some workload processes are executed on the source processor set and some workload processes are executed on a second processor set of processor units. Then, some workload processes are allocated to the second processor set so that no workload process is executing on the source processor set and at least some of said processes are executing on the second process set. The second processor set can be the target processor set or an intermediate processor set from which the workload is migrated to the target processor set.
    • 检测到要求将工作负载从源处理器集合处理单元迁移到处理单元集合的事件。 工作负载的处理被分配给处理单元的第二处理器集合,使得在源处理器集上执行一些工作负载过程,并且在第二处理器单元集合上执行一些工作负载过程。 然后,一些工作负载过程被分配给第二处理器集,使得在源处理器集上不执行工作负载过程,并且至少一些所述进程在第二进程集上执行。 第二处理器集合可以是目标处理器集合或中间处理器集合,工作负载从该集中迁移到目标处理器集合。
    • 9. 发明授权
    • Multiprocessor system with interactive synchronization of local clocks
    • 具有本地时钟交互式同步的多处理器系统
    • US07340630B2
    • 2008-03-04
    • US10638696
    • 2003-08-08
    • Dale C. MorrisJonathan K. Ross
    • Dale C. MorrisJonathan K. Ross
    • G06F1/04G06F1/12
    • G06F1/14H04J3/0638
    • A multiprocessor computer system comprises multiple data processors, each with an internal clock for providing time stamps to application software. The processors take turns as synchronization masters. The present master transmits a “request” time stamp (indicating the time of transmission according to the local clock) to the other (“slave”) processors. Each slave processor responds by returning a “response” time stamp (indicating the time of transmission of the response according to the local slave clock) of its own along with the received request time stamp. The master calculates clock adjustment values from the time of receipt of the responses and the included time stamps. This allows asynchronous clocks to be synchronized so that application time stamps can be validly compared across processors.
    • 多处理器计算机系统包括多个数据处理器,每个数据处理器具有用于向应用软件提供时间戳的内部时钟。 处理器轮流作为同步主机。 本主机向另一个(“从”)处理器发送“请求”时间戳(指示根据本地时钟发送的时间)。 每个从属处理器通过根据接收到的请求时间戳返回一个“响应”时间戳(指示根据本地从属时钟发送响应的时间)。 主人从接收到响应时间和包含的时间戳计算时钟调整值。 这允许异步时钟被同步,以便可以在处理器之间有效地比较应用程序时间戳。
    • 10. 发明授权
    • Advanced load address table entry invalidation based on register address wraparound
    • 基于注册地址环绕的高级加载地址表条目无效
    • US06631460B1
    • 2003-10-07
    • US09559508
    • 2000-04-27
    • Dale C. MorrisWilliam R. BryAlan H. KarpWilliam Chen
    • Dale C. MorrisWilliam R. BryAlan H. KarpWilliam Chen
    • G06T930
    • G06F9/3834G06F9/30127G06F9/3842
    • A computer system includes physical registers holding data for compiled programs and a portion of the physical registers form a register stack which wraps around when full. An N-bit current wraparound count state tracks physical register remapping events which cause the register stack to wraparound or unwrap. An advanced load address table (ALAT) has entries corresponding to load instructions, each entry has at least one memory range field defining a range of memory locations accessed by a corresponding load instruction, a physical register number field corresponding to a physical register accessed in the corresponding load instruction, and an N-bit register wraparound field which corresponds to the N-bit current wraparound count state for the corresponding load instruction. A check instruction accesses the ALAT to determine whether a store instruction and an advanced load instruction, which is scheduled before the store instruction, potentially accessed a common memory location. After the execution of the store instruction, an absence of an entry corresponding to the load instruction in the ALAT indicates that a common memory location may have been accessed by the store and load instructions.
    • 计算机系统包括保存用于已编译程序的数据的物理寄存器,并且部分物理寄存器形成寄存器堆栈,其在满地时包围。 N位当前环绕计数状态跟踪导致寄存器堆栈环绕或解开的物理寄存器重映射事件。 高级加载地址表(ALAT)具有对应于加载指令的条目,每个条目具有至少一个存储器范围字段,其定义由相应的加载指令访问的存储器位置的范围,对应于物理寄存器访问的物理寄存器号字段 相应的加载指令和对应于相应加载指令的N位当前环绕计数状态的N位寄存器环绕字段。 检查指令访问ALAT以确定在存储指令之前调度的存储指令和高级加载指令是否潜在地访问公共存储器位置。 在执行存储指令之后,没有与ALAT中的加载指令相对应的条目指示可以通过存储和加载指令访问公共存储器位置。