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1. 发明授权

US09298465B2 Asynchronous lookahead hierarchical branch prediction 有权
标题翻译：异步前瞻分层分支预测
公开(公告)号：US09298465B2
公开(公告)日：2016-03-29
申请号：US13524311
申请日：2012-06-15
申请人： James J. Bonanno , Akash V. Giri , Ulrich Mayer , Brian R. Prasky
发明人： James J. Bonanno , Akash V. Giri , Ulrich Mayer , Brian R. Prasky
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3806 , G06F9/30047 , G06F9/30145 , G06F9/3808
摘要： Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a system for asynchronous lookahead hierarchical branch prediction. The system includes a first-level branch target buffer and a second-level branch target buffer coupled to a processing circuit. The processing circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with a search address, and searching for an entry corresponding to the search request in the first-level branch target buffer. Based on failing to locate a matching entry in the first-level branch target buffer corresponding to the search request, a secondary search is initiated to locate entries in the second-level branch target buffer having a memory region corresponding to the search request. Based on locating the entries in the second-level branch target buffer, a bulk transfer of the entries is performed from the second-level branch target buffer.
摘要翻译：实施例涉及异步前瞻分层分支预测。一个方面包括用于异步前瞻分层分支预测的系统。该系统包括耦合到处理电路的第一级分支目标缓冲器和第二级分支目标缓冲器。处理电路被配置为执行一种方法。该方法包括接收搜索请求以定位与搜索地址相关联的分支预测信息，并且搜索与第一级分支目标缓冲器中的搜索请求相对应的条目。基于对与搜索请求相对应的第一级分支目标缓冲器中的匹配条目未定位，启动辅助搜索以定位具有对应于搜索请求的存储器区域的第二级分支目标缓冲器中的条目。基于在二级分支目标缓冲器中定位条目，从第二级分支目标缓冲器执行条目的批量传送。

2. 发明申请

US20130339695A1 ASYNCHRONOUS LOOKAHEAD SECOND LEVEL BRANCH TARGET BUFFER 有权
标题翻译：不寻常的LOOKAHEAD第二级分支目标缓冲区
公开(公告)号：US20130339695A1
公开(公告)日：2013-12-19
申请号：US13524311
申请日：2012-06-15
申请人： James J. Bonanno , Akash V. Giri , Ulrich Mayer , Brian R. Prasky
发明人： James J. Bonanno , Akash V. Giri , Ulrich Mayer , Brian R. Prasky
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30047 , G06F9/30145 , G06F9/3808
摘要： Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a system for asynchronous lookahead hierarchical branch prediction. The system includes a first-level branch target buffer and a second-level branch target buffer coupled to a processing circuit. The processing circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with a search address, and searching for an entry corresponding to the search request in the first-level branch target buffer. Based on failing to locate a matching entry in the first-level branch target buffer corresponding to the search request, a secondary search is initiated to locate entries in the second-level branch target buffer having a memory region corresponding to the search request. Based on locating the entries in the second-level branch target buffer, a bulk transfer of the entries is performed from the second-level branch target buffer.
摘要翻译：实施例涉及异步前瞻分层分支预测。一个方面包括用于异步前瞻分层分支预测的系统。该系统包括耦合到处理电路的第一级分支目标缓冲器和第二级分支目标缓冲器。处理电路被配置为执行一种方法。该方法包括接收搜索请求以定位与搜索地址相关联的分支预测信息，并且搜索与第一级分支目标缓冲器中的搜索请求相对应的条目。基于对与搜索请求相对应的第一级分支目标缓冲器中的匹配条目未定位，启动辅助搜索以定位具有与搜索请求对应的存储区域的第二级分支目标缓冲器中的条目。基于在二级分支目标缓冲器中定位条目，从第二级分支目标缓冲器执行条目的批量传送。

3. 发明授权

US08533394B2 Controlling simulation of a microprocessor instruction fetch unit through manipulation of instruction addresses 失效
公开(公告)号：US08533394B2
公开(公告)日：2013-09-10
申请号：US13399816
申请日：2012-02-17
申请人： Akash V. Giri , Darin M. Greene , Alan G. Singletary
发明人： Akash V. Giri , Darin M. Greene , Alan G. Singletary
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F11/2226
摘要： Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched.

4. 发明授权

US08478940B2 Controlling simulation of a microprocessor instruction fetch unit through manipulation of instruction addresses 失效
标题翻译：通过操纵指令地址来控制微处理器指令提取单元的仿真
公开(公告)号：US08478940B2
公开(公告)日：2013-07-02
申请号：US12476477
申请日：2009-06-02
申请人： Akash V. Giri , Darin M. Greene , Alan G. Singletary
发明人： Akash V. Giri , Darin M. Greene , Alan G. Singletary
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F11/2226
摘要： Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched.
摘要翻译：通过动态监视IFU模型的当前状态并检测任何预定的感兴趣状态来改善指令提取单元（IFU）验证。指令地址序列被自动修改，以迫使IFU模型接下来要获取选定的地址。可以通过插入一个或多个新的指令地址，或通过跳转到指令地址序列中的非顺序地址来修改指令地址序列。在示例性实现中，所选择的地址是已经加载到IFU高速缓存中的现有指令的对应地址，或者仅在特定字段中与该地址不同。优选地，通过向IFU模型发送刷新信号并覆盖对应于要获取的下一个地址的地址寄存器来实现指令地址控制，而不违反处理器架构的任何规则。

5. 发明申请

US20120151186A1 CONTROLLING SIMULATION OF A MICROPROCESSOR INSTRUCTION FETCH UNIT THROUGH MANIPULATION OF INSTRUCTION ADDRESSES 失效
标题翻译：通过操纵指令地址控制微处理器指令设备单元的仿真
公开(公告)号：US20120151186A1
公开(公告)日：2012-06-14
申请号：US13399816
申请日：2012-02-17
申请人： Akash V. Giri , Darin M. Greene , Alan G. Singletary
发明人： Akash V. Giri , Darin M. Greene , Alan G. Singletary
IPC分类号： G06F9/30 , G06F9/32
CPC分类号： G06F11/2226
摘要： Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched.
摘要翻译：通过动态监视IFU模型的当前状态并检测任何预定的感兴趣状态来改善指令提取单元（IFU）验证。指令地址序列被自动修改，以迫使IFU模型接下来要获取选定的地址。可以通过插入一个或多个新的指令地址，或通过跳转到指令地址序列中的非顺序地址来修改指令地址序列。在示例性实现中，所选择的地址是已经加载到IFU高速缓存中的现有指令的对应地址，或者仅在特定字段中与该地址不同。优选地，通过向IFU模型发送刷新信号并覆盖对应于要获取的下一个地址的地址寄存器来实现指令地址控制，而不违反处理器架构的任何规则。

6. 发明申请

US20100306476A1 CONTROLLING SIMULATION OF A MICROPROCESSOR INSTRUCTION FETCH UNIT THROUGH MANIPULATION OF INSTRUCTION ADDRESSES 失效
标题翻译：通过操纵指令地址控制微处理器指令设备单元的仿真
公开(公告)号：US20100306476A1
公开(公告)日：2010-12-02
申请号：US12476477
申请日：2009-06-02
申请人： Akash V. Giri , Darin M. Greene , Alan G. Singletary
发明人： Akash V. Giri , Darin M. Greene , Alan G. Singletary
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F11/2226
摘要： Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched.
摘要翻译：通过动态监视IFU模型的当前状态并检测任何预定的感兴趣状态来改善指令提取单元（IFU）验证。指令地址序列被自动修改，以迫使IFU模型接下来要获取选定的地址。可以通过插入一个或多个新的指令地址，或通过跳转到指令地址序列中的非顺序地址来修改指令地址序列。在示例性实现中，所选择的地址是已经加载到IFU高速缓存中的现有指令的对应地址，或者仅在特定字段中与该地址不同。优选地，通过向IFU模型发送刷新信号并覆盖对应于要获取的下一个地址的地址寄存器来实现指令地址控制，而不违反处理器架构的任何规则。

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