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1. 发明授权

US5426376A Noise isolated I/O buffer that uses two separate power supplies 失效
标题翻译：使用两个独立电源的噪声隔离I / O缓冲器
公开(公告)号：US5426376A
公开(公告)日：1995-06-20
申请号：US52442
申请日：1993-04-23
申请人： Jeffrey F. Wong , Derwin W. Mattos , James D. Shiffer, II
发明人： Jeffrey F. Wong , Derwin W. Mattos , James D. Shiffer, II
IPC分类号： H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/094 , H03K19/0948
CPC分类号： H03K19/00361 , H03K19/09429
摘要： An I/O buffer is provided that is noise-isolated, i.e., less susceptible to the effect of switching noise. In particular, a noise isolated I/O buffer includes an output terminal, a transient switching circuit connected to first power and ground voltage sources, to a logic input signal and to the output terminal, and a logic holding circuit connected to second power and ground voltage sources separate from the first power ground voltage sources, to the logic input signal and to the output terminal. The transient switching circuit causes a logic level of the output terminal to be switched responsive to a change in the input signal. The logic holding circuit causes the logic level of the output terminal to be maintained in the absence of a change in the input signal. In the absence of a change in the input signal, the transient switching circuit may be turned off, therefore presenting a high impedance to the first power and ground voltage sources. Switching noise in the first power supply network therefore is not transmitted through to the outputs of unswitched I/O buffers. The transient switching circuit and the logic holding circuit may be connected to the same power and ground voltage sources. The transient switching circuit, however, is turned off in the absence of a change in the input signal, and the logic holding circuit is turned off responsive to a change in the input signal. Smaller current surges are therefore provided at different times rather than a single large current surge, thereby reducing dI/dt.
摘要翻译：提供了噪声隔离的I / O缓冲器，即不易受切换噪声的影响。特别地，噪声隔离I / O缓冲器包括输出端子，连接到第一电源和地电压源的瞬态开关电路到逻辑输入信号和输出端，以及连接到第二电源和地的逻辑保持电路电压源与第一电源地电压源分离，到逻辑输入信号和输出端。瞬态切换电路使输出端子的逻辑电平响应于输入信号的变化而被切换。逻辑保持电路使得输入端子的逻辑电平在输入信号没有变化的情况下被维持。在没有输入信号变化的情况下，瞬态开关电路可能被关断，因此对第一电源和地电压源呈现高阻抗。因此，第一电源网络中的开关噪声不会传输到未切换的I / O缓冲器的输出。瞬态开关电路和逻辑保持电路可以连接到相同的电源和地电压源。然而，瞬态开关电路在输入信号没有变化的情况下被关断，并且逻辑保持电路响应于输入信号的变化而被截止。因此，在不同时间提供较小的电流浪涌，而不是单个大电流浪涌，从而减少dI / dt。

2. 发明授权

US5534791A Noise isolated I/O buffer 失效
公开(公告)号：US5534791A
公开(公告)日：1996-07-09
申请号：US375741
申请日：1995-01-20
申请人： Derwin W. Mattos , James D. Shiffer, II , Jeffrey F. Wong
发明人： Derwin W. Mattos , James D. Shiffer, II , Jeffrey F. Wong
IPC分类号： H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/094 , H03K19/0948
CPC分类号： H03K19/00361 , H03K19/09429
摘要： An I/O buffer is provided that is noise-isolated, i.e., less susceptible to the effect of switching noise. In particular, a noise isolated I/O buffer includes an output terminal, a transient switching circuit connected to first power and ground voltage sources, to a logic input signal and to the output terminal, and a logic holding circuit connected to second power and ground voltage sources separate from the first power ground voltage sources, to the logic input signal and to the output terminal. The transient switching circuit causes a logic level of the output terminal to be switched responsive to a change in the input signal. The logic holding circuit causes the logic level of the output terminal to be maintained in the absence of a change in the input signal. In the absence of a change in the input signal, the transient switching circuit may be turned off, therefore presenting a high impedance to the first power and ground voltage sources. Switching noise in the first power supply network therefore is not transmitted through to the outputs of unswitched I/O buffers. The transient switching circuit and the logic holding circuit may be connected to the same power and ground voltage sources. The transient switching circuit, however, is turned off in the absence of a change in the input signal, and the logic holding circuit is turned off responsive to a change in the input signal. Smaller current surges are therefore provided at different times rather than a single large current surge, thereby reducing dI/dt. Provision is made for delaying turn on of the logic holding circuit until a logic transition of the output signal is substantially complete, further reducing the effects of switching noise on unswitched outputs. Preferably, the logic holding circuit, once it has been turned on, remains on despite possible changes in the output voltage level and is turned off only in response to changes in the input signal. The transient switching circuit may be constructed so as to, once it has been turned off, remain off despite possible changes in the output voltage level, or to turn back on in order to help return to output voltage to the proper level.

3. 发明授权

US5287321A Illegal address detector for semiconductor memories 失效
标题翻译：用于半导体存储器的非法地址检测器
公开(公告)号：US5287321A
公开(公告)日：1994-02-15
申请号：US825489
申请日：1992-01-24
申请人： James D. Shiffer, II
发明人： James D. Shiffer, II
IPC分类号： G06F11/00 , G11C8/20 , G11C13/00
CPC分类号： G06F11/0763 , G11C8/20
摘要： When a user requests a RAM or other semiconductor memory to be compiled with a number of rows that is not a power of two, the compiler creates the RAM with one extra row. The rows requested by the user are placed at contiguous row addresses starting at zero and ending at one less than the number of rows requested. The highest of these row addresses is placed permanently in a comparator by the compiler. The comparator then compares each row address input to the RAM to the row address contained in the comparator. If the row address input is higher, then the comparator selects the extra row. The extra row can be written into or read from in the same manner as any other row in the RAM. The delay of the comparator is comparable to the delay of the address decoder, so that the RAM operates within the same specifications regardless of whether the address decoder selects a row or the comparator selects the extra row.
摘要翻译：当用户请求RAM或其他半导体存储器以不是2的幂数的行编译时，编译器创建一个额外的行的RAM。用户请求的行被放置在从零开始的连续行地址处，并以比所请求的行数少一个结束。这些行地址中最高的位置由编译器永久放置在比较器（18,20,24,26,28,30,32和34）中。比较器比较输入到RAM的每一行地址与比较器中包含的行地址。如果行地址输入较高，则比较器选择延伸行。额外的行可以以与RAM中的任何其他行相同的方式写入或读取。比较器的延迟与地址解码器的延迟相当，使得RAM在相同的规范中操作，而不管地址解码器是选择一行还是比较器选择额外的行。

4. 发明授权

US5313079A Gate array bases with flexible routing 失效
标题翻译：门阵列基座，灵活布线
公开(公告)号：US5313079A
公开(公告)日：1994-05-17
申请号：US953032
申请日：1992-09-25
申请人： Daniel R. Brasen , James D. Shiffer, II , Mark R. Hartoog , Sunil Asktaputre
发明人： Daniel R. Brasen , James D. Shiffer, II , Mark R. Hartoog , Sunil Asktaputre
IPC分类号： H01L27/118 , H01L27/10
CPC分类号： H01L27/11807 , Y10S257/909
摘要： Flexible routing of gate arrays increases routing efficiency, provides for the routing of functional blocks with other gates in the gate array, and provides structures for flexible power routing, particularly of gate arrays having functional blocks. In particular, a gate-array-implemented integrated circuit is designed using a computer by representing in computer memory a gate array base, placing gate array cells on the gate array base in placement rows each having a uniform height and separated by routing channels in which no gate array cells are placed, and routing in the routing channel connections between placement rows according to a netlist, during routing increasing the size of a routing channel if required and decreasing the size of a routing channel if possible by changing the placement of at least one placement row by an amount less than half the height of the placement row. Routing channel size is therefore flexibly adjusted "on-the-fly" during routing, increasing routing efficiency. The adjustment of routing channels in small (5 track) increments is made possible by defining "tall" macros (four transistor rows high) made of "small" (5 track high) transistors.
摘要翻译：门阵列的灵活路由提高了路由效率，为门阵列中的其他门提供了功能块的路由，并提供了灵活的功率路由结构，特别是具有功能块的门阵列。特别地，使用计算机设计的门阵列实现的集成电路通过在计算机存储器中表示门阵列基座，将门阵列单元放置在栅阵列基底上，每个放置行具有均匀的高度，并由路由通道分开，没有门阵列单元被放置，并且根据网表在路由信道中在布置行之间的连接中的路由，在路由期间增加路由信道的大小（如果需要），如果可能的话减小路由信道的大小，至少改变至少的位置一个展示位置行的数量少于展示位置行高度的一半。因此，路由通道的大小可以在路由过程中“即时”灵活调整，从而提高路由效率。通过定义由“小”（5轨高））晶体管制成的“高”宏（四个晶体管行高），可以实现小（5轨）增量的路由通道调整。

5. 发明授权

US6066962A Digital integrated circuit buffer digital device and method for buffering data 失效
标题翻译：数字集成电路缓冲数字设备及缓冲数据的方法
公开(公告)号：US6066962A
公开(公告)日：2000-05-23
申请号：US885052
申请日：1997-06-30
申请人： James D. Shiffer, II , Jeffrey F. Wong
发明人： James D. Shiffer, II , Jeffrey F. Wong
IPC分类号： H03K19/003 , H03K17/16 , H03K19/175
CPC分类号： H03K19/00315
摘要： The present invention provides digital integrated circuits, buffers, digital devices and methods for buffering data. One embodiment of the digital integrated circuit comprises: a data input configured to receive an input signal at a first voltage; a data output configured to output an output signal at a second voltage; a controller coupled with the data input and the controller being configured to generate an internal control signal and an external control signal responsive to the input signal; the controller having a first voltage regulator configured to maintain the external control signal above a threshold and a feedback voltage regulator configured to maintain the internal control signal above a threshold; and an output driver coupled with the data output and the controller, the output driver being configured to apply the output signal to the data output responsive to the external control signal.
摘要翻译：本发明提供了用于缓冲数据的数字集成电路，缓冲器，数字装置和方法。数字集成电路的一个实施例包括：数据输入，被配置为以第一电压接收输入信号; 数据输出，被配置为以第二电压输出输出信号; 与所述数据输入端耦合的控制器，所述控制器被配置为响应于所述输入信号产生内部控制信号和外部控制信号; 所述控制器具有被配置为将所述外部控制信号保持在阈值以上的第一电压调节器和配置成将所述内部控制信号保持在阈值以上的反馈电压调节器; 以及与数据输出和控制器耦合的输出驱动器，输出驱动器被配置为响应于外部控制信号将输出信号施加到数据输出。

6. 发明授权

US5343058A Gate array bases with flexible routing 失效
标题翻译：门阵列基座，灵活布线
公开(公告)号：US5343058A
公开(公告)日：1994-08-30
申请号：US902183
申请日：1992-06-22
申请人： James D. Shiffer, II
发明人： James D. Shiffer, II
IPC分类号： H01L27/118 , H01L27/10 , H01L23/48
CPC分类号： H01L27/11807 , H01L2924/0002
摘要： A transparent power grid is formed using a first metal layer and a second metal layer in a gate array having defined therein well tie-down regions. The first metal layer includes first power supply busses for supplying operating and reference voltages to the transistors, the first power supply busses extending in a row direction and overlapping the well tie-down region. The second metal layer includes second power supply busses for supplying operating and reference voltages to the transistors, the second power supply busses extending in a column direction and overlapping the well tie-down regions and the first power supply busses. Vias are formed where first and second power supply busses each supplying a same one of the operating voltage and the reference voltage overlap, thereby connecting the first and second power supply busses. Contacts are formed where first and second power supply busses each supplying a different one of the operating voltage and the reference voltage overlap, the contacts connecting the first power supply busses to underlying well tie-down regions. In effect, all of the necessary vias and contacts are placed in locations that in the prior art were all occupied by contacts alone.
摘要翻译：透明电网使用第一金属层和栅极阵列中的第二金属层形成，其中限定了阱结合区域。第一金属层包括用于向晶体管提供工作和参考电压的第一电源总线，第一电源总线沿着行方向延伸并与阱紧固区重叠。第二金属层包括用于向晶体管提供工作和参考电压的第二电源总线，第二电源总线在列方向上延伸并与阱结合区域和第一电源总线重叠。形成通道，其中每个提供相同的工作电压和参考电压的第一和第二电源总线重叠，从而连接第一和第二电源总线。在第一和第二电源总线各自提供工作电压和参考电压重叠的不同的第一和第二电源总线之间形成触点，所述触头将第一电源总线连接到下面的阱固定区域。实际上，所有必要的通孔和触点放置在现有技术中都被单独占据的位置。

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