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1. 发明授权

US07263627B2 System and method having strapping with override functions 有权
标题翻译：具有覆盖功能的系统和方法
公开(公告)号：US07263627B2
公开(公告)日：2007-08-28
申请号：US10641103
申请日：2003-08-15
申请人： James D Sweet , Thu T Nguyen
发明人： James D Sweet , Thu T Nguyen
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00
CPC分类号： H04N21/426 , H04N5/4401 , H04N5/46 , H04N7/035 , H04N21/4263 , H04N2005/91364
摘要： A system and method allow for overriding of a strapping option. A strapping signal places a device (e.g., a processor) in first state or mode (e.g., client or master). An override system places the device in a second state or mode. The second state or mode can be temporary. The changing of the state or mode of the device can be used to perform testing of the chip, during which a memory is written to and read from to verify operation of the chip. The second state or mode of the device may also be used to allow the device to perform alternative functions that are not available during its first state or mode.
摘要翻译：系统和方法允许覆盖捆绑选项。捆扎信号将设备（例如，处理器）置于第一状态或模式（例如，客户端或主机）。覆盖系统将设备置于第二状态或模式。第二种状态或模式可以是临时的。可以使用设备的状态或模式的改变来执行芯片的测试，在此期间，存储器被写入和读取以验证芯片的操作。设备的第二状态或模式也可以用于允许设备执行在其第一状态或模式期间不可用的替代功能。

2. 发明授权

US07532648B2 System and method using an I/O multiplexer module 有权
标题翻译：使用I / O复用器模块的系统和方法
公开(公告)号：US07532648B2
公开(公告)日：2009-05-12
申请号：US10640649
申请日：2003-08-14
申请人： James D Sweet
发明人： James D Sweet
IPC分类号： H04J3/04
CPC分类号： H04N21/426 , H04N5/4401 , H04N5/46 , H04N7/035 , H04N21/4263 , H04N2005/91364
摘要： A system (e.g., a chip) includes first and second function blocks (e.g., function blocks) coupled to an input/output (I/O) device (e.g., a bi-directional pin or pad) via a multiplexing module. The multiplexing module can be used for both input and output of signals between the function blocks and the I/O device. Optionally, a re-clocking system is coupled to the function blocks, the I/O device, and the multiplexing module. The re-clocking system re-clocks one or more signals being input into the multiplexing module so that they are timed correctly for input or output from the system.
摘要翻译：系统（例如，芯片）包括经由复用模块耦合到输入/输出（I / O）设备（例如，双向引脚或焊盘）的第一和第二功能块（例如，功能块）。复用模块可用于功能块和I / O设备之间的信号输入和输出。可选地，重新计时系统耦合到功能块，I / O设备和多路复用模块。重新计时系统将输入到复用模块中的一个或多个信号重新计时，使得它们被正确地定时输入或输出系统。

3. 发明授权

US07260166B2 Systems for synchronizing resets in multi-clock frequency applications 有权
标题翻译：用于在多时钟频率应用中同步复位的系统
公开(公告)号：US07260166B2
公开(公告)日：2007-08-21
申请号：US10640632
申请日：2003-08-14
申请人： James D Sweet
发明人： James D Sweet
IPC分类号： H04L7/00
CPC分类号： H04N21/426 , H04N5/4401 , H04N5/46 , H04N7/035 , H04N21/4263 , H04N2005/91364
摘要： Methods and systems for synchronizing a reset signal with a local clock that drives a circuit. In the circuit, the reset signal can be used to reset one or more flip-flops, memory devices, and/or logic. Sychronization of the reset signal allows the reset signal to change at an appropriate time period in relation to the lock clock signal driving the circuit. This ensures the circuit will remain stable during reset, and no data will be lost as it is processed in the circuit. Other aspects of the invention can include using a plurality of reset signals (e.g., software, hardware, local software, etc.) to form the reset signal and using a reset control system to control resets during testing of the circuit.
摘要翻译：将复位信号与驱动电路的本地时钟同步的方法和系统。在电路中，复位信号可用于复位一个或多个触发器，存储器件和/或逻辑。复位信号的同步允许复位信号相对于驱动电路的锁定时钟信号在适当的时间段改变。这确保电路在复位期间保持稳定，并且在电路中处理时不会丢失任何数据。本发明的其他方面可以包括使用多个复位信号（例如，软件，硬件，本地软件等）来形成复位信号，并且使用复位控制系统在电路测试期间控制复位。

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