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1. 发明申请

US20050280135A1 Stacking system and method 有权
标题翻译：堆叠系统和方法
公开(公告)号：US20050280135A1
公开(公告)日：2005-12-22
申请号：US11197267
申请日：2005-08-04
申请人： Russell Rapport , James Cady , James Wilder , David Roper , James Wehrly , Jeff Buchle , Julian Dowden
发明人： Russell Rapport , James Cady , James Wilder , David Roper , James Wehrly , Jeff Buchle , Julian Dowden
IPC分类号： H01L21/44 , H01L23/31 , H01L23/498 , H01L23/50 , H01L23/538 , H01L25/065 , H01L25/10 , H05K1/14 , H05K1/18 , H05K3/36
CPC分类号： H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/50 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/15173 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/0401
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the other. The two CSPs are connected with flex circuitry. A form standard is disposed between the flex circuitry and a CSP in the stack. The form standard can take many configurations and may be used where flex circuits are used to connect CSPs to one another in stacked modules having two or more constituent CSPs. For example, in stacked modules that include four CSPs, three form standards are employed in preferred embodiments, although fewer may be used. The form standard provides a thermally conductive physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.
摘要翻译：本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。在根据本发明的优选实施例设计的两高CSP堆叠或模块中，堆叠两个CSP，其中一个CSP设置在另一个之上。两个CSP与柔性电路连接。在柔性电路和堆叠中的CSP之间设置一个形式标准。形式标准可以采用许多配置，并且可以在柔性电路用于在具有两个或更多个组成CSP的堆叠模块中将CSP彼此连接的位置中使用。例如，在包括四个CSP的堆叠模块中，在优选实施例中采用三个形式标准，尽管可以使用更少的标准。形式标准提供导热物理形式，允许在广泛的CSP封装系列中找到许多变化的封装尺寸，同时采用标准连接柔性电路设计。

2. 发明申请

US20060131716A1 Stacking system and method 审中-公开
公开(公告)号：US20060131716A1
公开(公告)日：2006-06-22
申请号：US11317425
申请日：2005-12-22
申请人： James Cady , James Wilder , David Roper , James Wehrly , Julian Dowden , Jeff Buchle
发明人： James Cady , James Wilder , David Roper , James Wehrly , Julian Dowden , Jeff Buchle
IPC分类号： H01L23/12
CPC分类号： H05K1/141 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/01087 , H01L2924/19041 , H01L2924/3011 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734
摘要： The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.

3. 发明申请

US20050018412A1 Pitch change and chip scale stacking system 有权
标题翻译：间距变换和芯片级堆叠系统
公开(公告)号：US20050018412A1
公开(公告)日：2005-01-27
申请号：US10914483
申请日：2004-08-09
申请人： David Roper , James Cady , James Wilder , James Wehrly , Jeff Buchle , Julian Dowden
发明人： David Roper , James Cady , James Wilder , James Wehrly , Jeff Buchle , Julian Dowden
IPC分类号： H01L23/31 , H01L23/498 , H01L23/538 , H01L25/10 , H05K1/14 , H05K1/18 , H05K3/36
CPC分类号： H01L23/49816 , H01L23/3114 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734
摘要： The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and its application environment. The module has a ballout pattern with a different pitch and/or supplemental module contacts devised to allow combined signaling to the integrated circuits through contacts having a desired ballout footprint. The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.
摘要翻译：本发明将集成电路堆叠成节省电路板表面积的模块。在根据本发明的优选实施例设计的两高堆叠或模块中，堆叠一对集成电路，一个集成电路在另一个之上。两个集成电路与一对柔性电路结构连接。一对柔性电路结构中的每一个部分地缠绕在模块的下部集成电路的相应的相对侧边缘上。柔性电路对连接上下集成电路，并在模块与其应用环境之间提供热和电路连接路径。模块具有不同间距和/或补充模块触点的布置图案，其设计为允许通过具有期望的展开占位面积的触点对集成电路的组合信令。本发明可以有利于提供用于高密度存储器或高容量计算的模块中的集成电路的多种配置和组合。

4. 发明申请

US20050146011A1 Pitch change and chip scale stacking system and method 有权
标题翻译：间距变换和芯片级堆叠系统及方法
公开(公告)号：US20050146011A1
公开(公告)日：2005-07-07
申请号：US11074026
申请日：2005-03-08
申请人： David Roper , James Cady , James Wilder , James Wehrly , Jeff Buchle , Julian Dowden
发明人： David Roper , James Cady , James Wilder , James Wehrly , Jeff Buchle , Julian Dowden
IPC分类号： H01L23/31 , H01L23/498 , H01L23/538 , H01L25/10 , H05K1/14 , H05K1/18 , H05K3/36 , H01L23/02
CPC分类号： H01L23/49816 , H01L23/3114 , H01L23/49827 , H01L23/4985 , H01L23/5386 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/0002 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/058 , H05K2201/10734 , H01L2924/0001
摘要： The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and its application environment. The module has a bailout pattern with a different pitch and/or supplemental module contacts devised to allow combined signaling to the integrated circuits through contacts having a desired bailout footprint. The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.
摘要翻译：本发明将集成电路堆叠成节省电路板表面积的模块。在根据本发明的优选实施例设计的两高堆叠或模块中，堆叠一对集成电路，一个集成电路在另一个之上。两个集成电路与一对柔性电路结构连接。一对柔性电路结构中的每一个部分地缠绕在模块的下部集成电路的相应的相对侧边缘上。柔性电路对连接上下集成电路，并在模块与其应用环境之间提供热和电路连接路径。该模块具有一个具有不同间距和/或补充模块触点的救援模式，用于允许通过具有期望的救助足迹的触点向集成电路组合发信号。本发明可以有利于提供用于高密度存储器或高容量计算的模块中的集成电路的多种配置和组合。

5. 发明申请

US20060091521A1 Stacking system and method 审中-公开
公开(公告)号：US20060091521A1
公开(公告)日：2006-05-04
申请号：US11316505
申请日：2005-12-21
申请人： James Cady , James Wilder , David Roper , James Wehrly , Julian Dowden , Jeff Buchle
发明人： James Cady , James Wilder , David Roper , James Wehrly , Julian Dowden , Jeff Buchle
IPC分类号： H01L23/48
CPC分类号： H05K1/141 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/01087 , H01L2924/19041 , H01L2924/3011 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734
摘要： The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.

6. 发明申请

US20050057911A1 Memory expansion and integrated circuit stacking system and method 有权
标题翻译：内存扩展和集成电路堆叠系统及方法
公开(公告)号：US20050057911A1
公开(公告)日：2005-03-17
申请号：US10804452
申请日：2004-03-19
申请人： Russell Rapport , James Cady , James Wilder , David Roper , James Wehrly , Jeff Buchle
发明人： Russell Rapport , James Cady , James Wilder , David Roper , James Wehrly , Jeff Buchle
IPC分类号： H01L25/065 , H01L25/10 , H05K7/06 , H01L23/538
CPC分类号： H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/107 , H01L2924/3011 , H01L2924/00012
摘要： The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.
摘要翻译：本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。在根据本发明的优选实施例中，形式标准提供了一种物理形式，其允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计时被有利地使用。在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。在存储器寻址系统的优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载影响。

7. 发明申请

US20050062144A1 Memory expansion and chip scale stacking system and method 失效
标题翻译：内存扩展和芯片级堆叠系统及方法
公开(公告)号：US20050062144A1
公开(公告)日：2005-03-24
申请号：US10963867
申请日：2004-10-12
申请人： Russell Rapport , James Cady , James Wilder , David Roper , James Wehrly , Jeff Buchle
发明人： Russell Rapport , James Cady , James Wilder , David Roper , James Wehrly , Jeff Buchle
IPC分类号： H01L21/44 , H01L23/31 , H01L23/498 , H01L23/50 , H01L23/538 , H01L25/065 , H01L25/10 , H05K1/14 , H05K1/18 , H05K3/36 , H01L23/02
CPC分类号： H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/50 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/15173 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/0401
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.
摘要翻译：本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。在根据本发明的优选实施例中，形式标准被布置在柔性电路和IC封装之间，柔性电路的一部分放置在该IC封装上。形式标准提供了一种物理形式，允许在采用标准连接柔性电路设计时，在广泛的CSP封装系列中发现许多变化的封装尺寸。在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。在优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载效应。这有利地改变了堆叠模块的DIMM板所呈现的阻抗特性。在优选实施例中，例如在逻辑控制下的FET多路复用器选择与填充在DIMM上的特定级别的堆叠模块相关联的特定数据线，以连接到存储器扩展系统中的控制芯片。

8. 发明申请

US20080067662A1 Modularized Die Stacking System and Method 审中-公开
标题翻译：模块化堆叠系统和方法
公开(公告)号：US20080067662A1
公开(公告)日：2008-03-20
申请号：US11941718
申请日：2007-11-16
申请人： David Roper , Curtis Hart , James Wilder , Phill Bradley , James Cady , Jeff Buchle , James Wehrly
发明人： David Roper , Curtis Hart , James Wilder , Phill Bradley , James Cady , Jeff Buchle , James Wehrly
IPC分类号： H01L23/14 , H01L21/58 , H05K1/00
CPC分类号： H05K1/147 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L24/48 , H01L25/105 , H01L2224/05599 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/45099 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2224/73215 , H01L2224/85399 , H01L2225/1058 , H01L2924/00014 , H01L2924/01322 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19107 , H01L2924/3011 , H05K1/141 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： An IC die and a flexible circuit structure are integrated into a lower stack element that can be stacked with either further integrated lower stack element iterations or with pre-packaged ICs in any of a variety of package types. A die is positioned above the surface of portions of a pair of flex circuits. Connection is made between the die and the flex circuitry. A protective layer is formed to protect the flex-connected die and its connection to the flex. Connective elements are placed along the flex circuitry to create an array of module contacts along the second side of the flex circuitry. The flex circuitry is positioned above the body-protected die to create an integrated lower stack element. The integrated lower stack element may be stacked either with iterations of the integrated lower stack element or with a pre-packaged IC to create a multi-element stacked circuit module.
摘要翻译：集成电路芯片和柔性电路结构被集成到下层堆叠元件中，该堆叠元件可以进一步集成的下堆叠元件迭代或者以各种封装类型中的任何一种封装的预先封装的IC堆叠。模具位于一对柔性电路的部分的表面上方。在管芯和柔性电路之间进行连接。形成保护层以保护弯曲连接的模具及其与柔性件的连接。连接元件沿着柔性电路放置，以沿柔性电路的第二侧创建一组模块触点。柔性电路位于身体保护的模具上方，以形成集成的下层叠元件。集成的下堆叠元件可以通过集成的下堆叠元件的迭代或者与预先封装的IC堆叠以产生多元件堆叠电路模块。

9. 发明申请

US20050067683A1 Memory expansion and chip scale stacking system and method 审中-公开
公开(公告)号：US20050067683A1
公开(公告)日：2005-03-31
申请号：US10978149
申请日：2004-10-29
申请人： Russell Rapport , James Cady , James Wilder , David Roper , James Wehrly , Jeff Buchle
发明人： Russell Rapport , James Cady , James Wilder , David Roper , James Wehrly , Jeff Buchle
IPC分类号： H01L21/44 , H01L23/31 , H01L23/498 , H01L23/50 , H01L23/538 , H01L25/065 , H01L25/10 , H05K1/14 , H05K1/18 , H05K3/36 , H01L23/02
CPC分类号： H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/50 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/15173 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/0401
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.

10. 发明授权

US06618257B1 Wide data path stacking system and method 有权
标题翻译：宽数据路径堆叠系统和方法
公开(公告)号：US06618257B1
公开(公告)日：2003-09-09
申请号：US09916625
申请日：2001-07-27
申请人： James Cady , David L. Roper , James G. Wilder , Julian Dowden , Jeff Buchle
发明人： James Cady , David L. Roper , James G. Wilder , Julian Dowden , Jeff Buchle
IPC分类号： H05K700
CPC分类号： H05K1/141 , H05K1/182 , H05K3/3426 , H05K2201/049 , H05K2201/10386 , H05K2201/10515 , H05K2201/10689 , H05K2203/1572
摘要： Provided is a system and method for selectively stacking and interconnecting integrated circuit devices having a data path of n-bits to create a high-density integrated circuit module having a data path of greater than n-bits. Integrated circuits are vertically stacked one above the other. Where the constituent IC elements have a data path of n-bits in width, a module devised in accordance with a preferred embodiment of the present invention presents a data path 2n-bits wide. In a preferred embodiment, an interconnection frame comprised of printed circuit board material is disposed about two similarly oriented ICs to provide interconnectivity of the constituent ICs and concatenation of their respective data paths. An array of clip-leads or other connectors are appended to module connection pads to provide lead-like structures for connection of the module to its operating environment. In a two-high stack, address lines of the constituent ICs are interconnected, while the data lines of the respective ICs are concatenated to double the data path width of the stack relative to the data path width of the constituent ICs. In an alternative preferred embodiment, two facially juxtaposed TSOP ICs are surface mounted to an interconnection body laterally positioned between the ICs. The interconnection body has IC connection pads and a set of module connection pads for connection of the module. The interconnection body has a network of connections that interconnects the address lines of the constituent ICs and concatenates the data lines to double the data path width of the stack relative to the data path width of the ICs from which the stack is composed.
摘要翻译：提供了一种用于选择性地堆叠和互连具有n位数据路径的集成电路器件以产生具有大于n位数据路径的高密度集成电路模块的系统和方法。集成电路垂直堆叠在一起。在构成IC元件具有宽度为n位的数据路径的情况下，根据本发明的优选实施例设计的模块呈现2n位宽的数据路径。在优选实施例中，由印刷电路板材料构成的互连框架围绕两个类似定向的IC设置，以提供组成IC的互连性和它们各自的数据路径的级联。夹子引线或其他连接器的阵列被附加到模块连接焊盘，以提供用于将模块连接到其操作环境的引线状结构。在两高堆叠中，组成IC的地址线互连，而相应IC的数据线相对于组成IC的数据路径宽度被连接到堆叠的数据路径宽度的两倍。在替代的优选实施例中，两个面向并置的TSOP IC被表面安装到侧向位于IC之间的互连体。互连体具有IC连接焊盘和用于连接模块的一组模块连接焊盘。互连体具有连接组成IC的地址线的连接网络，并且将数据线连接成相对于组成堆栈的IC的数据路径宽度将堆栈的数据路径宽度加倍。

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