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1. 发明授权

US09299707B2 Three-dimensional semiconductor devices with current path selection structure 有权
标题翻译：具有电流路径选择结构的三维半导体器件
公开(公告)号：US09299707B2
公开(公告)日：2016-03-29
申请号：US14150452
申请日：2014-01-08
申请人： Jaeduk Lee , Youngwoo Park , Jintaek Park , Dohyun Lee , Kohji Kanamori
发明人： Jaeduk Lee , Youngwoo Park , Jintaek Park , Dohyun Lee , Kohji Kanamori
IPC分类号： H01L27/108 , H01L27/105 , H01L27/115 , G11C16/10 , G11C16/14
CPC分类号： H01L27/1052 , G11C16/10 , G11C16/14 , H01L27/11524 , H01L27/11556
摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.
摘要翻译：提供三维半导体器件及其操作方法。三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。

2. 发明申请

US20140197469A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICES WITH CURRENT PATH SELECTION STRUCTURE AND METHODS OF OPERATING THE SAME 有权
标题翻译：具有电流路径选择结构的三维半导体器件及其操作方法
公开(公告)号：US20140197469A1
公开(公告)日：2014-07-17
申请号：US14150452
申请日：2014-01-08
申请人： Jaeduk Lee , Youngwoo Park , Jintaek Park , Dohyun Lee , Kohji Kanamori
发明人： Jaeduk Lee , Youngwoo Park , Jintaek Park , Dohyun Lee , Kohji Kanamori
IPC分类号： H01L27/105
CPC分类号： H01L27/1052 , G11C16/10 , G11C16/14 , H01L27/11524 , H01L27/11556
摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.
摘要翻译：提供三维半导体器件及其操作方法。三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。

3. 发明授权

US09183893B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09183893B2
公开(公告)日：2015-11-10
申请号：US14037547
申请日：2013-09-26
申请人： Kohji Kanamori , Youngwoo Park , Jintaek Park , Kwang Soo Seol , Jaeduk Lee
发明人： Kohji Kanamori , Youngwoo Park , Jintaek Park , Kwang Soo Seol , Jaeduk Lee
IPC分类号： G11C5/06 , G11C13/00 , H01L45/00 , H01L27/22 , H01L27/24
CPC分类号： G11C5/06 , G11C5/063 , G11C13/0002 , G11C13/0023 , G11C2213/73 , H01L27/222 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147
摘要： According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.
摘要翻译：根据本发明构思的示例性实施例，半导体存储器件包括：多个存储器块，每个存储块包括多个堆叠结构，共同连接到多个存储器块的全局位线，被配置为控制全局位线和多个存储器块中的一个以及垂直选择线，其被配置为控制连接在全局位线和多个堆叠结构中的一个之间的电连接。多个堆叠结构中的每一个包括多个局部位线，第一垂直字线和第二垂直字线，其横向于多个堆叠结构的第一侧壁和第二侧壁相交，多个堆叠结构之间的第一可变电阻元件和第一垂直字线和第二可变电阻元件在多个堆叠结构和第二垂直字线之间。

4. 发明授权

US09224429B2 Three-dimensional semiconductor devices and methods of fabricating the same 有权
公开(公告)号：US09224429B2
公开(公告)日：2015-12-29
申请号：US14635588
申请日：2015-03-02
申请人： Jintaek Park , Kohji Kanamori , Youngwoo Park , Jaeduk Lee
发明人： Jintaek Park , Kohji Kanamori , Youngwoo Park , Jaeduk Lee
IPC分类号： G11C5/02 , H01L27/115 , G11C7/02 , G11C7/18 , G11C7/10
CPC分类号： G11C5/025 , G11C7/02 , G11C7/1039 , G11C7/18 , H01L27/11573 , H01L27/11582
摘要： According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.

5. 发明授权

US09019739B2 Three-dimensional semiconductor devices and methods of fabricating the same 有权
标题翻译：三维半导体器件及其制造方法
公开(公告)号：US09019739B2
公开(公告)日：2015-04-28
申请号：US14152440
申请日：2014-01-10
申请人： Jintaek Park , Kohji Kanamori , Youngwoo Park , Jaeduk Lee
发明人： Jintaek Park , Kohji Kanamori , Youngwoo Park , Jaeduk Lee
IPC分类号： G11C5/02 , H01L27/115 , G11C7/02 , G11C7/18 , G11C7/10
CPC分类号： G11C5/025 , G11C7/02 , G11C7/1039 , G11C7/18 , H01L27/11573 , H01L27/11582
摘要： According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.
摘要翻译：根据本发明构思的示例性实施例，三维半导体器件可以包括：存储单元阵列，其包括可以三维布置的存储器单元，所述存储单元阵列包括与右侧相对的左侧，平面图的底面; 与存储单元阵列的左侧和右侧中的至少一个相邻的至少一个字线解码器; 邻近存储单元阵列的底侧的页缓冲器; 以及与存储单元阵列的顶侧和底侧之一相邻的串选择线解码器。

6. 发明授权

US09960171B2 Semiconductor devices including charge storage patterns 有权
公开(公告)号：US09960171B2
公开(公告)日：2018-05-01
申请号：US15245540
申请日：2016-08-24
申请人： Kohji Kanamori , Shinhwan Kang , Youngwoo Park , Junghoon Park
发明人： Kohji Kanamori , Shinhwan Kang , Youngwoo Park , Junghoon Park
IPC分类号： H01L27/115 , H01L29/788 , H01L29/792 , H01L27/11519 , H01L27/11565 , H01L27/11556 , H01L27/11582 , H01L27/11524 , H01L27/1157
CPC分类号： H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： Semiconductor devices are provided. A semiconductor device includes a plurality of gate electrodes. The semiconductor device includes a channel structure adjacent the plurality of gate electrodes. The semiconductor device includes a plurality of charge storage segments between the channel structure and the plurality of gate electrodes. Methods of forming semiconductor devices are also provided.

7. 发明申请

US20170125428A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
公开(公告)号：US20170125428A1
公开(公告)日：2017-05-04
申请号：US15245540
申请日：2016-08-24
申请人： Kohji Kanamori , Shinhwan Kang , Youngwoo Park , Junghoon Park
发明人： Kohji Kanamori , Shinhwan Kang , Youngwoo Park , Junghoon Park
IPC分类号： H01L27/115 , H01L29/792 , H01L29/788
CPC分类号： H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： Semiconductor devices are provided. A semiconductor device includes a plurality of gate electrodes. The semiconductor device includes a channel structure adjacent the plurality of gate electrodes. The semiconductor device includes a plurality of charge storage segments between the channel structure and the plurality of gate electrodes. Methods of forming semiconductor devices are also provided.

8. 发明授权

US10396092B2 Vertical memory device and method of manufacturing the same 有权
公开(公告)号：US10396092B2
公开(公告)日：2019-08-27
申请号：US15455778
申请日：2017-03-10
申请人： Kohji Kanamori , Dong-Seog Eun
发明人： Kohji Kanamori , Dong-Seog Eun
IPC分类号： H01L27/00 , H01L27/11582 , H01L27/1157 , H01L27/11565
摘要： Disclosed are vertical memory devices and methods of manufacturing the same. The vertical memory device may include includes a substrate, a gate stack structure and channel structure on the substrate, and a charge trap structure between the gate stack structure and the channel structure. The gate stack structure includes conductive structures and insulation interlayer structures that are alternately stacked on each other in a vertical direction on the substrate such that cell regions and inter-cell regions are alternately arranged in the vertical direction. The channel structure penetrates through the gate stack structure in the vertical direction. The charge trap structure and the conductive structures define memory cells at the cell regions. The charge structure is configured to selectively store charges. The charge trap structure includes an anti-coupling structure in the inter-cell region for reducing a coupling between neighboring memory cells adjacent to each other in the vertical direction.

9. 发明授权

US08039940B2 Semiconductor storage device, semiconductor device, and manufacturing method therefor 有权
标题翻译：半导体存储装置，半导体装置及其制造方法
公开(公告)号：US08039940B2
公开(公告)日：2011-10-18
申请号：US11956358
申请日：2007-12-14
申请人： Kohji Kanamori , Teiichirou Nishizaka , Noriaki Kodama , Isao Katayama , Yoshihiro Matsuura , Kaoru Ishihara , Yasushi Harada , Naruaki Minenaga , Chihiro Oshita
发明人： Kohji Kanamori , Teiichirou Nishizaka , Noriaki Kodama , Isao Katayama , Yoshihiro Matsuura , Kaoru Ishihara , Yasushi Harada , Naruaki Minenaga , Chihiro Oshita
IPC分类号： H01L23/26
CPC分类号： H01L23/26 , H01L21/3221 , H01L23/3128 , H01L24/48 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/12032 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.
摘要翻译：根据本发明，在半导体芯片的侧表面和底表面上沉积吸气层。然后将半导体芯片安装在封装的板上，使得在底表面上形成肖特基势垒。通过这种结构，可以通过沉积在半导体芯片的侧表面和/或底表面上的缺陷层和肖特基势垒捕获穿过封装板的金属离子。

10. 发明授权

US07880214B2 Nonvolatile semiconductor device 有权
标题翻译：非易失性半导体器件
公开(公告)号：US07880214B2
公开(公告)日：2011-02-01
申请号：US11431569
申请日：2006-05-11
申请人： Naoaki Sudo , Kohji Kanamori
发明人： Naoaki Sudo , Kohji Kanamori
IPC分类号： H01L29/76
CPC分类号： H01L29/7887 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor storage device in which one unit cell comprises a select gate 3 (3a-3i) provided in a first region on a substrate 1; a floating gate 6 provided in a second region adjacent to the first region; a diffused region 7b adjacent to the second region and provided in a third region on the surface of the substrate 1; and a control gate 11 provided on the floating gate 6. The select gate 3 is divided into three or more in an erase block 23 composed of all unit cells, from each of which electrons are extracted from the floating gate, at the same time when an erase operation is performed. Each of the select gates 3a-3i, created by the division, is formed in a comb-like shape in which, when viewed from the direction of a normal line to a plane, a plurality of comb teeth extend from a common line. The comb teeth of a select gate (for example, 3b) are arranged in gaps between the comb teeth of an adjacent select gate (for example, 3a, 3c) at a predetermined spacing.
摘要翻译：一种非易失性半导体存储装置，其中一个单位电池包括设置在基板1上的第一区域中的选择栅极3（3a-3i）设置在与第一区域相邻的第二区域中的浮动栅极6; 与第二区域相邻并设置在基板1的表面的第三区域中的扩散区域7b; 以及设置在浮置栅极6上的控制栅极11.选择栅极3在由所有单位单元构成的擦除块23中被划分为三个或更多个，其中每一个从浮置栅极中提取电子，同时当执行擦除操作。通过分割产生的选择门3a-3i中的每一个形成为梳状形状，其中从法线方向看平面时，多条梳齿从公共线延伸。选择门（例如3b）的梳齿以预定间隔布置在相邻选择栅极（例如，3a，3c）的梳齿之间的间隙中。

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