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1. 发明授权

US07679960B2 Non-volatile memory device and method of operating the same 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US07679960B2
公开(公告)日：2010-03-16
申请号：US11980358
申请日：2007-10-31
申请人： Jae-woong Hyun , Kyu-charn Park , Yoon-dong Park , Won-joo Kim , Young-gu Jin , Suk-pil Kim , Kyoung-Iae Cho , Jung-hoon Lee , Seung-hwan Song
发明人： Jae-woong Hyun , Kyu-charn Park , Yoon-dong Park , Won-joo Kim , Young-gu Jin , Suk-pil Kim , Kyoung-Iae Cho , Jung-hoon Lee , Seung-hwan Song
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L27/1203
摘要： A highly integrated non-volatile memory device and a method of operating the non-volatile memory device are provided. The non-volatile memory device includes a semiconductor layer. A plurality of upper control gate electrodes are arranged above the semiconductor layer. A plurality of lower control gate electrodes are arranged below the semiconductor layer, and the plurality of upper control gate electrodes and the plurality of lower control gate electrodes are disposed alternately. A plurality of upper charge storage layers are interposed between the semiconductor layer and the upper control gate electrodes. A plurality of lower charge storage layers are interposed between the semiconductor layer and the lower control gate electrodes.
摘要翻译：提供高度集成的非易失性存储器件和操作非易失性存储器件的方法。非易失性存储器件包括半导体层。多个上控制栅电极设置在半导体层的上方。多个下部控制栅电极配置在半导体层的下方，多个上部控制栅极电极和多个下部控制栅极电极交替配置。多个上电荷存储层插入在半导体层和上控制栅电极之间。多个下电荷存储层插入在半导体层和下控制栅电极之间。

2. 发明申请

US20080151631A1 Non-volatile memory device and method of operating the same 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20080151631A1
公开(公告)日：2008-06-26
申请号：US11980358
申请日：2007-10-31
申请人： Jae-woong Hyun , Kyu-charn Park , Yoon-dong Park , Won-joo Kim , Young-gu Jin , Suk-pil Kim , Kyoung-lae Cho , Jung-hoon Lee , Seung-hwan Song
发明人： Jae-woong Hyun , Kyu-charn Park , Yoon-dong Park , Won-joo Kim , Young-gu Jin , Suk-pil Kim , Kyoung-lae Cho , Jung-hoon Lee , Seung-hwan Song
IPC分类号： G11C16/06 , H01L29/788
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L27/1203
摘要： A highly integrated non-volatile memory device and a method of operating the non-volatile memory device are provided. The non-volatile memory device includes a semiconductor layer. A plurality of upper control gate electrodes are arranged above the semiconductor layer. A plurality of lower control gate electrodes are arranged below the semiconductor layer, and the plurality of upper control gate electrodes and the plurality of lower control gate electrodes are disposed alternately. A plurality of upper charge storage layers are interposed between the semiconductor layer and the upper control gate electrodes. A plurality of lower charge storage layers are interposed between the semiconductor layer and the lower control gate electrodes.
摘要翻译：提供高度集成的非易失性存储器件和操作非易失性存储器件的方法。非易失性存储器件包括半导体层。多个上控制栅电极设置在半导体层的上方。多个下部控制栅电极配置在半导体层的下方，多个上部控制栅极电极和多个下部控制栅极电极交替配置。多个上电荷存储层插入在半导体层和上控制栅电极之间。多个下电荷存储层插入在半导体层和下控制栅电极之间。

3. 发明申请

US20070019479A1 Semiconductor device and random access memory having single gate electrode corresponding to a pair of channel regions 有权
标题翻译：具有对应于一对通道区域的单个栅电极的半导体器件和随机存取存储器
公开(公告)号：US20070019479A1
公开(公告)日：2007-01-25
申请号：US11393750
申请日：2006-03-31
申请人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
发明人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
IPC分类号： G11C7/10
CPC分类号： H01L29/66795 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/11507 , H01L27/2436 , H01L29/785
摘要： A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.
摘要翻译：半导体器件可以包括半导体衬底上的至少一对散热片。可以在每个鳍中形成沟道区。半导体器件还可以包括对应于每对沟道区的栅电极，同时电连接到形成在相应散热片上的至少一个源中的每一个的源极接触插塞以及电连接到至少一个漏斗同时形成在相应的翅片上。

4. 发明授权

US07352037B2 Semiconductor device and random access memory having single gate electrode corresponding to a pair of channel regions 有权
标题翻译：具有对应于一对通道区域的单个栅电极的半导体器件和随机存取存储器
公开(公告)号：US07352037B2
公开(公告)日：2008-04-01
申请号：US11393750
申请日：2006-03-31
申请人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
发明人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
IPC分类号： H01L29/94
CPC分类号： H01L29/66795 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/11507 , H01L27/2436 , H01L29/785
摘要： A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.
摘要翻译：半导体器件可以包括半导体衬底上的至少一对散热片。可以在每个鳍中形成沟道区。半导体器件还可以包括对应于每对沟道区的栅电极，同时电连接到形成在相应散热片上的至少一个源中的每一个的源极接触插塞以及电连接到至少一个漏斗同时形成在相应的翅片上。

5. 发明申请

US20080315285A1 Non-volatile memory devices and methods of fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080315285A1
公开(公告)日：2008-12-25
申请号：US12071452
申请日：2008-02-21
申请人： Tae-hee Lee , Jae-woong Hyun , Ju-hee Park , In-kyeong Yoo , Yoon-dong Park , Won-joo Kim , Jung-hoon Lee
发明人： Tae-hee Lee , Jae-woong Hyun , Ju-hee Park , In-kyeong Yoo , Yoon-dong Park , Won-joo Kim , Jung-hoon Lee
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42336
摘要： Non-volatile memory devices and methods of fabricating the same are provided. The non-volatile memory devices may include a semiconductor substrate having a pair of sidewall channel regions extending from the semiconductor substrate and opposite to each other, and a floating gate electrode between the pair of sidewall channel regions and protruding from the semiconductor substrate. A control gate electrode may be formed on the semiconductor substrate and a portion of the floating gate electrode.
摘要翻译：提供非易失性存储器件及其制造方法。非易失性存储器件可以包括具有从半导体衬底延伸并且彼此相对的一对侧壁沟道区的半导体衬底，以及在该对侧壁沟道区之间并从半导体衬底突出的浮置栅电极。控制栅电极可以形成在半导体衬底和浮栅电极的一部分上。

6. 发明授权

US07622765B2 Non-volatile memory device and a method of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07622765B2
公开(公告)日：2009-11-24
申请号：US11709057
申请日：2007-02-22
申请人： Won-joo Kim , Yoon-dong Park , Jung-hoon Lee
发明人： Won-joo Kim , Yoon-dong Park , Jung-hoon Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11519 , H01L29/42332 , H01L29/792
摘要： A non-volatile memory device and a method of fabricating the same are provided. A non-volatile memory device may include a semiconductor substrate including a body and at least one pair of fins vertically protruding from the body and spaced apart from each other, and at least one control gate electrode on at least portions of outer side surfaces of the at least one pair of fins and extending onto top portions of the at least one pair of fins on an angle with the at least one pair of fins. The non-volatile memory device may further include at least one pair of gate insulating layers between the at least one control gate electrode and the at least one pair of fins, and at least one pair of storage node layers between the at least one pair of gate insulating layers and at least a portion of the at least one control gate electrode. The at least one control gate electrode may extend onto top portions of the at least one pair of fins in a zigzag fashion.
摘要翻译：提供了一种非易失性存储器件及其制造方法。非易失性存储器件可以包括半导体衬底，其包括主体和从主体垂直突出并且彼此间隔开的至少一对鳍，以及至少一个控制栅电极，其位于至少一个的外侧表面的至少部分上至少一对翅片，并且与所述至少一对翅片成角度地延伸到所述至少一对翅片的顶部上。非易失性存储器件还可以包括至少一对控制栅电极与至少一对散热片之间的至少一对栅绝缘层，以及至少一对控制栅电极之间的至少一对存储节点层栅绝缘层和至少一个控制栅电极的至少一部分。至少一个控制栅极可以以锯齿形的方式延伸到至少一对翅片的顶部。

7. 发明授权

US07535049B2 Multi bits flash memory device and method of operating the same 失效
标题翻译：多位闪存器件及其操作方法
公开(公告)号：US07535049B2
公开(公告)日：2009-05-19
申请号：US11249393
申请日：2005-10-14
申请人： Won-joo Kim , Yoon-dong Park , Eun-hong Lee , Sun-ae Seo , Sang-min Shin , Jung-hoon Lee , Seung-hyuk Chang
发明人： Won-joo Kim , Yoon-dong Park , Eun-hong Lee , Sun-ae Seo , Sang-min Shin , Jung-hoon Lee , Seung-hyuk Chang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： G11C11/5621 , B82Y10/00 , G11C11/5607 , G11C11/5628 , G11C11/5657 , G11C13/025 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L29/0692 , H01L29/4232 , H01L29/7923
摘要： A multi bits flash memory device and a method of operating the same are disclosed. The multi bits flash memory device includes: a stacked structure including: a first active layer with a mesa-like form disposed on a substrate; a second active layer, having a different conductivity type from the first active layer, formed on the first active layer; an active interlayer isolation layer interposed between the first active layer and the second active layer such that the first active layer is electrically isolated from the second active layer; a common source and a common drain formed on a pair of opposite side surfaces of the stacked structure; a common first gate and a common second gate formed on the other pair of opposite side surfaces of the stacked structure; a tunnel dielectric layer interposed between the first and second gates and the first and second active layers; and a charge trap layer, storing charges that tunnel through the tunnel dielectric layer, interposed between the tunnel dielectric layer and the first and second gates.
摘要翻译：公开了一种多位闪存器件及其操作方法。多位闪存器件包括：堆叠结构，包括：设置在衬底上的具有台面状形状的第一有源层; 形成在所述第一有源层上的与所述第一有源层不同的导电类型的第二有源层; 插入在第一有源层和第二有源层之间的有源层间隔离层，使得第一有源层与第二有源层电隔离; 形成在所述堆叠结构的一对相对侧表面上的共同源极和共同漏极; 形成在所述堆叠结构的另一对相对侧表面上的公共第一栅极和公共第二栅极; 介于所述第一和第二栅极与所述第一和第二有源层之间的隧道介电层; 以及电荷捕获层，其存储穿过隧道介电层的电荷，介于隧道介电层和第一和第二栅极之间。

8. 发明申请

US20070284632A1 Non-volatile memory device and a method of fabricating the same 有权
公开(公告)号：US20070284632A1
公开(公告)日：2007-12-13
申请号：US11709057
申请日：2007-02-22
申请人： Won-joo Kim , Yoon-dong Park , Jung-hoon Lee
发明人： Won-joo Kim , Yoon-dong Park , Jung-hoon Lee
IPC分类号： H01L29/00
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11519 , H01L29/42332 , H01L29/792
摘要： A non-volatile memory device and a method of fabricating the same are provided. A non-volatile memory device may include a semiconductor substrate including a body and at least one pair of fins vertically protruding from the body and spaced apart from each other, and at least one control gate electrode on at least portions of outer side surfaces of the at least one pair of fins and extending onto top portions of the at least one pair of fins on an angle with the at least one pair of fins. The non-volatile memory device may further include at least one pair of gate insulating layers between the at least one control gate electrode and the at least one pair of fins, and at least one pair of storage node layers between the at least one pair of gate insulating layers and at least a portion of the at least one control gate electrode. The at least one control gate electrode may extend onto top portions of the at least one pair of fins in a zigzag fashion.

9. 发明申请

US20060097306A1 Multi bits flash memory device and method of operating the same 失效
公开(公告)号：US20060097306A1
公开(公告)日：2006-05-11
申请号：US11249393
申请日：2005-10-14
申请人： Won-joo Kim , Yoon-dong Park , Eun-hong Lee , Sun-ae Seo , Sang-min Shin , Jung-hoon Lee , Seung-hyuk Chang
发明人： Won-joo Kim , Yoon-dong Park , Eun-hong Lee , Sun-ae Seo , Sang-min Shin , Jung-hoon Lee , Seung-hyuk Chang
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： G11C11/5621 , B82Y10/00 , G11C11/5607 , G11C11/5628 , G11C11/5657 , G11C13/025 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L29/0692 , H01L29/4232 , H01L29/7923
摘要： A multi bits flash memory device and a method of operating the same are disclosed. The multi bits flash memory device includes: a stacked structure including: a first active layer with a mesa-like form disposed on a substrate; a second active layer, having a different conductivity type from the first active layer, formed on the first active layer; an active interlayer isolation layer interposed between the first active layer and the second active layer such that the first active layer is electrically isolated from the second active layer; a common source and a common drain formed on a pair of opposite side surfaces of the stacked structure; a common first gate and a common second gate formed on the other pair of opposite side surfaces of the stacked structure; a tunnel dielectric layer interposed between the first and second gates and the first and second active layers; and a charge trap layer, storing charges that tunnel through the tunnel dielectric layer, interposed between the tunnel dielectric layer and the first and second gates.

10. 发明授权

US08184473B2 Nanowire memory device and method of manufacturing the same 有权
公开(公告)号：US08184473B2
公开(公告)日：2012-05-22
申请号：US12872835
申请日：2010-08-31
申请人： Jin-gyoo Yoo , Cheol-soon Kim , Jung-hoon Lee
发明人： Jin-gyoo Yoo , Cheol-soon Kim , Jung-hoon Lee
IPC分类号： G11C11/50
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/16 , H01L51/0048 , Y10S977/943
摘要： A nanowire memory device and a method of manufacturing the same are provided. A memory device includes: a substrate; a first electrode formed on the substrate; a first nanowire extending from an end of the first electrode; a second electrode formed over the first electrode to overlap the first electrode; and a second nanowire extending from an end of the second electrode corresponding to the end of the first electrode in the same direction as the first nanowire, wherein an insulating layer exists between the first and second electrodes.

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