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1. 发明申请

US20130168800A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130168800A1
公开(公告)日：2013-07-04
申请号：US13717803
申请日：2012-12-18
申请人： Jae-Joo Shim , Han-Soo Kim , Woon-Kyung Lee , Ju-Young Lim , Sung-Min Hwang
发明人： Jae-Joo Shim , Han-Soo Kim , Woon-Kyung Lee , Ju-Young Lim , Sung-Min Hwang
IPC分类号： H01L29/06
CPC分类号： H01L29/0657 , H01L27/0207 , H01L27/1157 , H01L27/11582
摘要： Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.
摘要翻译：提供了包括设置在基板上的第一和第二隔离图案的半导体器件。交替层叠的层间绝缘图案和导电图案设置在第一和第二隔离图案之间的基板的表面上。支撑图案穿透导电图案和层间绝缘图案，并且具有比第一和第二隔离图案更小的宽度。第一和第二垂直结构设置在第一隔离和支撑图案之间并且穿透导电图案和层间绝缘图案。第二垂直结构设置在第二隔离图案和支撑图案之间并且穿透导电图案和层间绝缘图案。支撑图案的顶表面和底表面之间的距离大于支撑图案的底表面和基底表面之间的距离。

2. 发明授权

US09209244B2 Semiconductor device with vertical structures that penetrate conductive patterns and interlayer insulating patterns 有权
标题翻译：具有穿透导电图案和层间绝缘图案的垂直结构的半导体器件
公开(公告)号：US09209244B2
公开(公告)日：2015-12-08
申请号：US13717803
申请日：2012-12-18
申请人： Jae-Joo Shim , Han-Soo Kim , Woon-Kyung Lee , Ju-Young Lim , Sung-Min Hwang
发明人： Jae-Joo Shim , Han-Soo Kim , Woon-Kyung Lee , Ju-Young Lim , Sung-Min Hwang
IPC分类号： H01L29/06 , H01L27/02 , H01L27/115
CPC分类号： H01L29/0657 , H01L27/0207 , H01L27/1157 , H01L27/11582
摘要： Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.
摘要翻译：提供了包括设置在基板上的第一和第二隔离图案的半导体器件。交替层叠的层间绝缘图案和导电图案设置在第一和第二隔离图案之间的基板的表面上。支撑图案穿透导电图案和层间绝缘图案，并且具有比第一和第二隔离图案更小的宽度。第一和第二垂直结构设置在第一隔离和支撑图案之间并且穿透导电图案和层间绝缘图案。第二垂直结构设置在第二隔离图案和支撑图案之间并且穿透导电图案和层间绝缘图案。支撑图案的顶表面和底表面之间的距离大于支撑图案的底表面和基底表面之间的距离。

3. 发明授权

US09306041B2 Vertical type semiconductor devices 有权
标题翻译：垂直型半导体器件
公开(公告)号：US09306041B2
公开(公告)日：2016-04-05
申请号：US14156607
申请日：2014-01-16
申请人： Sung-Min Hwang , Han-Soo Kim , Woon-Kyung Lee , Won-Seok Cho
发明人： Sung-Min Hwang , Han-Soo Kim , Woon-Kyung Lee , Won-Seok Cho
IPC分类号： H01L29/66 , H01L29/792 , H01L27/115
CPC分类号： H01L29/66833 , H01L27/11575 , H01L27/11582 , H01L29/7926
摘要： A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines. Connecting patterns electrically connect pairs of adjacent first and second word lines in a same plane. The device may be a nonvolatile memory device or a different type of device.
摘要翻译：垂直型半导体器件包括包括第一和第二字线的第一和第二字线结构。字线围绕多个柱结构，其被提供以将字线连接到相应的字符串选择线。连接图案将相邻的第一和第二字线的对电连接在同一平面中。该设备可以是非易失性存储设备或不同类型的设备。

4. 发明授权

US09087861B2 Methods of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09087861B2
公开(公告)日：2015-07-21
申请号：US14156781
申请日：2014-01-16
申请人： Sung-Min Hwang , Han-Soo Kim , Woon-Kyung Lee , Won-Seok Cho
发明人： Sung-Min Hwang , Han-Soo Kim , Woon-Kyung Lee , Won-Seok Cho
IPC分类号： H01L21/336 , H01L29/66 , H01L29/792 , H01L27/115
CPC分类号： H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.
摘要翻译：制造垂直型存储装置的方法包括在基板上堆叠第一下绝缘层，一层下牺牲层和第二下绝缘层，通过堆叠牺牲层和绝缘层形成堆叠结构，并蚀刻边缘部分堆叠结构以形成初步的阶梯状图案结构。初步阶形形状图案结构具有阶梯形边缘部分。形成与基板表面接触的柱结构。部分地蚀刻初步阶形状图案结构，下牺牲层和第一下绝缘层和第二下绝缘层，以形成第一开口部分和第二开口部分，以形成台阶状图形结构。第二开口部分切割下牺牲层的至少边缘部分。

5. 发明申请

US20120256253A1 Vertical Memory Devices 审中-公开
标题翻译：垂直存储器件
公开(公告)号：US20120256253A1
公开(公告)日：2012-10-11
申请号：US13432485
申请日：2012-03-28
申请人： Sung-Min Hwang , Woon-Kyung Lee , Young-Jin Kwon , Tae-Hee Lee , Hui-Chang Moon
发明人： Sung-Min Hwang , Woon-Kyung Lee , Young-Jin Kwon , Tae-Hee Lee , Hui-Chang Moon
IPC分类号： H01L29/78
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/7827
摘要： Vertical memory devices include a channel, a ground selection line (GSL), a word line, a string selection line (SSL), a pad and an etch-stop layer. The channel extends in a first direction on a substrate. The channel includes an impurity region and the first direction is perpendicular to a top surface of the substrate. At least one GSL, a plurality of the word lines and at least one SSL are spaced apart from each other in the first direction on a sidewall of the channel. The pad is disposed on a top surface of the channel. The etch-stop layer contacts the pad.
摘要翻译：垂直存储器件包括通道，接地选择线（GSL），字线，串选择线（SSL），焊盘和蚀刻停止层。通道在基板上沿第一方向延伸。通道包括杂质区，第一方向垂直于衬底的顶表面。至少一个GSL，多个字线和至少一个SSL在信道的侧壁上沿第一方向彼此间隔开。衬垫设置在通道的顶表面上。蚀刻停止层接触焊盘。

6. 发明授权

US07851304B2 Nonvolatile memory device and fabrication method 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US07851304B2
公开(公告)日：2010-12-14
申请号：US11641869
申请日：2006-12-20
申请人： Woon-Kyung Lee , Jeong-Hyuk Choi
发明人： Woon-Kyung Lee , Jeong-Hyuk Choi
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S438/981
摘要： Provided is a nonvolatile memory device and a fabrication method. The nonvolatile memory device includes an active region defined in a semiconductor substrate, a gate insulating layer formed on the active region and a plurality of gate patterns formed on the gate insulating layer, and crossing over the active region. The gate insulating layer includes a discharge region in a predetermined portion between the gate patterns, the discharge region having a lesser thickness than that of the gate insulating layer under the gate pattern, because a thickness portion of the gate insulating layer is removed to form the discharge region.
摘要翻译：提供了一种非易失性存储器件和制造方法。非易失性存储器件包括限定在半导体衬底中的有源区，形成在有源区上的栅极绝缘层和形成在栅极绝缘层上并跨过有源区的多个栅极图案。栅极绝缘层包括在栅极图案之间的预定部分中的放电区域，由于栅极绝缘层的厚度部分被去除以形成栅极绝缘层的厚度部分，所以放电区域的厚度小于栅极图案下的栅极绝缘层的厚度。放电区域。

7. 发明申请

US20080096350A1 Nonvolatile memory device and fabrication method 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US20080096350A1
公开(公告)日：2008-04-24
申请号：US11641869
申请日：2006-12-20
申请人： Woon-Kyung Lee , Jeong-Hyuk Choi
发明人： Woon-Kyung Lee , Jeong-Hyuk Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S438/981
摘要： Provided is a nonvolatile memory device and a fabrication method. The nonvolatile memory device includes an active region defined in a semiconductor substrate, a gate insulating layer formed on the active region and a plurality of gate patterns formed on the gate insulating layer, and crossing over the active region. The gate insulating layer includes a discharge region in a predetermined portion between the gate patterns, the discharge region having a lesser thickness than that of the gate insulating layer under the gate pattern, because a thickness portion of the gate insulating layer is removed to form the discharge region.
摘要翻译：提供了一种非易失性存储器件和制造方法。非易失性存储器件包括限定在半导体衬底中的有源区，形成在有源区上的栅极绝缘层和形成在栅极绝缘层上并跨过有源区的多个栅极图案。栅极绝缘层包括在栅极图案之间的预定部分中的放电区域，由于栅极绝缘层的厚度部分被去除以形成栅极绝缘层的厚度部分，所以放电区域的厚度小于栅极图案下的栅极绝缘层的厚度。放电区域。

8. 发明申请

US20080079038A1 Semiconductor devices with gate insulation layers having different thicknesses and methods of forming the same 审中-公开
标题翻译：具有不同厚度的栅绝缘层的半导体器件及其形成方法
公开(公告)号：US20080079038A1
公开(公告)日：2008-04-03
申请号：US11646127
申请日：2006-12-27
申请人： Tae-Kyung Kim , Woon-Kyung Lee
发明人： Tae-Kyung Kim , Woon-Kyung Lee
IPC分类号： H01L29/76
CPC分类号： H01L21/2652 , H01L21/28123 , H01L21/28238 , H01L21/823462 , H01L21/823481 , H01L29/42368
摘要： Methods of forming a semiconductor device include an active region and a shallow trench isolation region in a semiconductor substrate, and forming a gate insulation layer on the active region. The gate insulation layer includes a first part spaced apart from the shallow trench isolation region and a second part adjacent the shallow trench isolation region and disposed between the shallow trench isolation region and the first part, and thicker than the first part. The methods further include forming a first impurity region in the active region of the semiconductor substrate adjacent the first part, and forming a gate line on the gate insulation layer. Corresponding semiconductor devices are also disclosed.
摘要翻译：形成半导体器件的方法包括半导体衬底中的有源区和浅沟槽隔离区，并且在有源区上形成栅极绝缘层。栅极绝缘层包括与浅沟槽隔离区域间隔开的第一部分和与浅沟槽隔离区域相邻并且设置在浅沟槽隔离区域和第一部分之间并且比第一部分更厚的第二部分。所述方法还包括在所述半导体衬底的与所述第一部分相邻的有源区中形成第一杂质区，以及在所述栅极绝缘层上形成栅极线。还公开了相应的半导体器件。

9. 发明申请

US20070001212A1 NAND-type memory devices including recessed source/drain regions and related methods 审中-公开
标题翻译： NAND型存储器件包括凹陷源极/漏极区域和相关方法
公开(公告)号：US20070001212A1
公开(公告)日：2007-01-04
申请号：US11431273
申请日：2006-05-10
申请人： Woon-Kyung Lee , Jeong-Hyuk Choi
发明人： Woon-Kyung Lee , Jeong-Hyuk Choi
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A NAND-type memory device may include first and second selection transistors on a semiconductor substrate and a plurality of memory cell transistors coupled in series between the first and second selection transistors. A first source/drain region may be shared between the first selection transistor and a first of the memory cell transistors, and a second source/drain region may be shared between the second selection transistor and a last of the memory cell transistors. Moreover, a portion of at least one of the first and/or second source/drain regions may be recessed relative to a surface of the semiconductor substrate. Related methods are also discussed.
摘要翻译： NAND型存储器件可以包括半导体衬底上的第一和第二选择晶体管和串联耦合在第一和第二选择晶体管之间的多个存储单元晶体管。第一源/漏区可以在第一选择晶体管和第一存储单元晶体管之间共享，并且第二源/漏区可以在第二选择晶体管和最后的存储单元晶体管之间共享。此外，第一和/或第二源极/漏极区域中的至少一个的一部分可以相对于半导体衬底的表面凹陷。还讨论了相关方法。

10. 发明申请

US20060231885A1 Semiconductor device and method of fabricating the same 有权
公开(公告)号：US20060231885A1
公开(公告)日：2006-10-19
申请号：US11455888
申请日：2006-06-20
申请人： Woon-Kyung Lee
发明人： Woon-Kyung Lee
IPC分类号： H01L29/76 , H01L29/00
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11534 , H01L27/11568
摘要： The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation film. A gate pattern is disposed between the word line and the active region, and a tunnel oxide film is disposed between the gate pattern and the active region. The gate pattern comprises a floating gate pattern, a gate interlayer dielectric film pattern and a control gate electrode pattern deposited in the respective order, and has a sidewall self-aligned to the device isolation film. To form the gate pattern having the sidewall self-aligned to the device isolation film, a gate insulation film and a gate material film are formed in the respective order on the semiconductor substrate.

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