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1. 发明授权

US07719033B2 Semiconductor devices having thin film transistors and methods of fabricating the same 有权
标题翻译：具有薄膜晶体管的半导体器件及其制造方法
公开(公告)号：US07719033B2
公开(公告)日：2010-05-18
申请号：US11364773
申请日：2006-02-28
申请人： Jae-Hun Jeong , Soon-Moon Jung , Hoon Lim , Won-Seok Cho , Jin-Ho Kim , Chang-Min Hong , Jong-Hyuk Kim , Kun-Ho Kwak
发明人： Jae-Hun Jeong , Soon-Moon Jung , Hoon Lim , Won-Seok Cho , Jin-Ho Kim , Chang-Min Hong , Jong-Hyuk Kim , Kun-Ho Kwak
IPC分类号： H01L29/74
CPC分类号： H01L27/0688 , H01L23/485 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having thin film transistors (TFTs) and methods of fabricating the same are provided. The semiconductor devices include a semiconductor substrate and a lower interlayer insulating layer disposed on the semiconductor substrate. A lower semiconductor body disposed on or in the lower interlayer insulating layer. A lower TFT includes a lower source region and a lower drain region, which are disposed in the lower semiconductor body, and a lower gate electrode, which covers and crosses at least portions of at least two surfaces of the lower semiconductor body disposed between the lower source and drain regions.
摘要翻译：提供具有薄膜晶体管（TFT）的半导体器件及其制造方法。半导体器件包括设置在半导体衬底上的半导体衬底和下层间绝缘层。下部半导体本体设置在下部层间绝缘层上或下部层间绝缘层中。下部TFT包括设置在下部半导体本体中的下部源极区域和下部漏极区域以及下部栅极电极，该下部栅极电极覆盖并交叉配置在下部半导体本体的下侧半导体本体的至少两个表面的至少一部分源极和漏极区域。

2. 发明申请

US20060237725A1 Semiconductor devices having thin film transistors and methods of fabricating the same 有权
标题翻译：具有薄膜晶体管的半导体器件及其制造方法
公开(公告)号：US20060237725A1
公开(公告)日：2006-10-26
申请号：US11364773
申请日：2006-02-28
申请人： Jae-Hun Jeong , Soon-Moon Jung , Hoon Lim , Won-Seok Cho , Jin-Ho Kim , Chang-Min Hong , Jong-Hyuk Kim , Kun-Ho Kwak
发明人： Jae-Hun Jeong , Soon-Moon Jung , Hoon Lim , Won-Seok Cho , Jin-Ho Kim , Chang-Min Hong , Jong-Hyuk Kim , Kun-Ho Kwak
IPC分类号： H01L29/76 , H01L29/00
CPC分类号： H01L27/0688 , H01L23/485 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having thin film transistors (TFTs) and methods of fabricating the same are provided. The semiconductor devices include a semiconductor substrate and a lower interlayer insulating layer disposed on the semiconductor substrate. A lower semiconductor body disposed on or in the lower interlayer insulating layer. A lower TFT includes a lower source region and a lower drain region, which are disposed in the lower semiconductor body, and a lower gate electrode, which covers and crosses at least portions of at least two surfaces of the lower semiconductor body disposed between the lower source and drain regions.
摘要翻译：提供具有薄膜晶体管（TFT）的半导体器件及其制造方法。半导体器件包括设置在半导体衬底上的半导体衬底和下层间绝缘层。下部半导体本体设置在下部层间绝缘层上或下部层间绝缘层中。下部TFT包括设置在下部半导体本体中的下部源极区域和下部漏极区域以及下部栅极电极，该下部栅极电极覆盖并交叉配置在下部半导体器件的下部半导体本体的至少两个表面的至少一部分源极和漏极区域。

3. 发明授权

US07709323B2 Methods of forming nand-type nonvolatile memory devices 有权
标题翻译：形成非易失性存储器件的方法
公开(公告)号：US07709323B2
公开(公告)日：2010-05-04
申请号：US12474896
申请日：2009-05-29
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.
摘要翻译：形成NAND型非易失性存储器件的方法包括：在半导体衬底中限定的有源区域中交替形成第一公共漏极和第一公共源，并延伸一个方向，形成覆盖半导体衬底的整个表面的第一绝缘层图案化第一绝缘层以形成以规则距离布置的暴露有源区域的种子接触孔，形成填充每个种子接触孔的种子接触结构以及设置在第一绝缘层上并接触种子接触的半导体层结构，图案化所述半导体层以形成在所述一个方向上延伸并设置在所述有源区上方的半导体图案，形成沿所述一个方向交替设置在所述半导体图案中的第二公共漏极和第二公共源，形成第二绝缘层覆盖层半导体衬底的整个表面使源极线图案连续地穿过第二绝缘层，半导体图案和第一绝缘层，源极线图案与第一和第二共用源连接，其中半导体层的晶界位于第二绝缘层之间的中心一对种子接触结构彼此相邻，并且位于第一公共漏极或第一公共源的上方。

4. 发明申请

US20090233405A1 METHODS OF FORMING NAND-TYPE NONVOLATILE MEMORY DEVICES 有权
标题翻译：形成NAND型非易失性存储器件的方法
公开(公告)号：US20090233405A1
公开(公告)日：2009-09-17
申请号：US12474896
申请日：2009-05-29
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.
摘要翻译：形成NAND型非易失性存储器件的方法包括：在半导体衬底中限定的有源区域中交替形成第一公共漏极和第一公共源，并延伸一个方向，形成覆盖半导体衬底的整个表面的第一绝缘层图案化第一绝缘层以形成以规则距离布置的暴露有源区域的种子接触孔，形成填充每个种子接触孔的种子接触结构以及设置在第一绝缘层上并接触种子接触的半导体层结构，图案化所述半导体层以形成在所述一个方向上延伸并设置在所述有源区上方的半导体图案，形成沿所述一个方向交替设置在所述半导体图案中的第二公共漏极和第二公共源，形成第二绝缘层覆盖层半导体衬底的整个表面使源极线图案连续地穿过第二绝缘层，半导体图案和第一绝缘层，源极线图案与第一和第二共用源连接，其中半导体层的晶界位于第二绝缘层之间的中心一对种子接触结构彼此相邻，并且位于第一公共漏极或第一公共源的上方。

5. 发明授权

US07554140B2 Nand-type non-volatile memory device 失效
标题翻译： Nand型非易失性存储器件
公开(公告)号：US07554140B2
公开(公告)日：2009-06-30
申请号：US11651892
申请日：2007-01-10
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L31/062
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.
摘要翻译：提供了一种NAND型非易失性存储器件及其形成方法。在该方法中，多个单元层层叠在半导体基板上。用于形成包含在层叠电池中的半导体图案的种子接触孔以规则的距离形成。此时，种子接触孔布置成使得位线插头或源极线图案设置在彼此相邻的一对种子接触孔之间的中心处。

6. 发明申请

US20080085582A1 Hand-type nonvolatile memory device and method of forming the same 失效
标题翻译：手持式非易失性存储装置及其形成方法
公开(公告)号：US20080085582A1
公开(公告)日：2008-04-10
申请号：US11651892
申请日：2007-01-10
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.
摘要翻译：提供了一种NAND型非易失性存储器件及其形成方法。在该方法中，多个单元层层叠在半导体基板上。用于形成包含在层叠电池中的半导体图案的种子接触孔以规则的距离形成。此时，种子接触孔布置成使得位线插头或源极线图案设置在彼此相邻的一对种子接触孔之间的中心处。

7. 发明申请

US20060049467A1 Body-tied-to-source MOSFETs with asymmetrical source and drain regions and methods of fabricating the same 有权
标题翻译：具有不对称源极和漏极区域的体耦对源MOSFET及其制造方法
公开(公告)号：US20060049467A1
公开(公告)日：2006-03-09
申请号：US11179236
申请日：2005-07-12
申请人： Hoon Lim , Soon-Moon Jung , Won-Seok Cho , Jae-Hun Jeong
发明人： Hoon Lim , Soon-Moon Jung , Won-Seok Cho , Jae-Hun Jeong
IPC分类号： H01L27/01
CPC分类号： H01L29/0847 , H01L21/743 , H01L27/11 , H01L27/1108 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7834 , H01L29/78612 , H01L29/78654
摘要： A metal oxide semiconductor field effect transistor (MOSFET) includes a body pattern of a first conductivity type disposed on an insulating layer. A gate electrode is disposed on the body pattern. A drain region of a second conductivity type is disposed on the insulating layer and having a sidewall in contact with a first sidewall of the body pattern. An impurity-doped region of the first conductivity type is disposed on the insulating layer and having a sidewall in contact with a second sidewall of the body pattern. The MOSFET further includes a source region of the second conductivity type disposed on the impurity-doped region and having a sidewall in contact with the second sidewall of the body pattern, and a contact plug extending through the source region to contact the impurity-doped region.
摘要翻译：金属氧化物半导体场效应晶体管（MOSFET）包括设置在绝缘层上的第一导电类型的主体图案。栅电极设置在主体图案上。第二导电类型的漏极区域设置在绝缘层上并且具有与主体图案的第一侧壁接触的侧壁。第一导电类型的杂质掺杂区域设置在绝缘层上并且具有与主体图案的第二侧壁接触的侧壁。 MOSFET还包括设置在杂质掺杂区域上并具有与主体图案的第二侧壁接触的侧壁的第二导电类型的源极区域，以及延伸穿过源极区域以接触杂质掺杂区域的接触插塞。

8. 发明授权

US07432560B2 Body-tied-to-source MOSFETs with asymmetrical source and drain regions and methods of fabricating the same 有权
标题翻译：具有不对称源极和漏极区域的体耦对源MOSFET及其制造方法
公开(公告)号：US07432560B2
公开(公告)日：2008-10-07
申请号：US11179236
申请日：2005-07-12
申请人： Hoon Lim , Soon-Moon Jung , Won-Seok Cho , Jae-Hun Jeong
发明人： Hoon Lim , Soon-Moon Jung , Won-Seok Cho , Jae-Hun Jeong
IPC分类号： H01L27/01
CPC分类号： H01L29/0847 , H01L21/743 , H01L27/11 , H01L27/1108 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7834 , H01L29/78612 , H01L29/78654
摘要： A metal oxide semiconductor field effect transistor (MOSFET) includes a body pattern of a first conductivity type disposed on an insulating layer. A gate electrode is disposed on the body pattern. A drain region of a second conductivity type is disposed on the insulating layer and having a sidewall in contact with a first sidewall of the body pattern. An impurity-doped region of the first conductivity type is disposed on the insulating layer and having a sidewall in contact with a second sidewall of the body pattern. The MOSFET further includes a source region of the second conductivity type disposed on the impurity-doped region and having a sidewall in contact with the second sidewall of the body pattern, and a contact plug extending through the source region to contact the impurity-doped region.
摘要翻译：金属氧化物半导体场效应晶体管（MOSFET）包括设置在绝缘层上的第一导电类型的主体图案。栅电极设置在主体图案上。第二导电类型的漏极区域设置在绝缘层上并且具有与主体图案的第一侧壁接触的侧壁。第一导电类型的杂质掺杂区域设置在绝缘层上并且具有与主体图案的第二侧壁接触的侧壁。 MOSFET还包括设置在杂质掺杂区域上并具有与主体图案的第二侧壁接触的侧壁的第二导电类型的源极区域，以及延伸穿过源极区域以接触杂质掺杂区域的接触插塞。

9. 发明授权

US08084306B2 Methods of forming semiconductor devices having self-aligned bodies 失效
标题翻译：形成具有自对准体的半导体器件的方法
公开(公告)号：US08084306B2
公开(公告)日：2011-12-27
申请号：US12409968
申请日：2009-03-24
申请人： Jae-Hun Jeong , Hoon Lim , Soon-Moon Jung , Hoo-Sung Cho
发明人： Jae-Hun Jeong , Hoon Lim , Soon-Moon Jung , Hoo-Sung Cho
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/783 , H01L29/78606 , H01L29/78654
摘要： A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the body region, and a body contact connects the gate pattern to the body region. A sidewall of the body region extension is self-aligned to a sidewall of the gate pattern. Methods of forming semiconductor devices having a self-aligned body and a body contact are also disclosed.
摘要翻译：半导体器件包括具有源极区域，漏极区域，插入在源极区域和漏极区域之间的沟道区域的主体区域以及从沟道区域的端部延伸的主体区域延伸部。在沟道区域和体区域上形成栅极图案，并且体接触将栅极图案连接到身体区域。身体区域延伸部的侧壁与栅极图案的侧壁自对准。还公开了具有自对准体和身体接触的半导体器件的形成方法。

10. 发明申请

US20060113599A1 Semiconductor devices having self-aligned bodies and methods of forming the same 审中-公开
标题翻译：具有自对准体的半导体器件及其形成方法
公开(公告)号：US20060113599A1
公开(公告)日：2006-06-01
申请号：US11233415
申请日：2005-09-22
申请人： Jae-Hun Jeong , Hoon Lim , Soon-Moon Jung , Hoo-Sung Cho
发明人： Jae-Hun Jeong , Hoon Lim , Soon-Moon Jung , Hoo-Sung Cho
IPC分类号： H01L27/12
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/783 , H01L29/78606 , H01L29/78654
摘要： A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the body region, and a body contact connects the gate pattern to the body region. A sidewall of the body region extension is self-aligned to a sidewall of the gate pattern. Methods of forming semiconductor devices having a self-aligned body and a body contact are also disclosed.
摘要翻译：半导体器件包括具有源极区域，漏极区域，插入在源极区域和漏极区域之间的沟道区域的主体区域以及从沟道区域的端部延伸的主体区域延伸部。在沟道区域和体区域上形成栅极图案，并且体接触将栅极图案连接到身体区域。身体区域延伸部的侧壁与栅极图案的侧壁自对准。还公开了具有自对准体和身体接触的半导体器件的形成方法。

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