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1. 发明授权

US5903508A Input buffer of memory device for reducing current consumption in standby mode 失效
标题翻译：存储器件的输入缓冲器，用于降低待机模式下的电流消耗
公开(公告)号：US5903508A
公开(公告)日：1999-05-11
申请号：US979227
申请日：1997-11-26
申请人： Jae Myoung Choi
发明人： Jae Myoung Choi
IPC分类号： G11C11/417 , G11C7/00 , G11C7/10 , G11C11/401 , G11C11/407 , G11C11/409
CPC分类号： G11C7/1093 , G11C7/1078
摘要： An input buffer of memory device for reducing current consumption in standby mode comprising a bus input buffer for inputting successive bus data signals through a bus and buffering the inputted bus data signals, and a flag buffer for generating a control signal in response to a system clock signal and a flag signal indicative of a bus data input time point to operate the bus input buffer before a first one of the bus data signals arrives at the bus input buffer and to allow the bus input buffer to enter a standby mode at once after the bus data signal input is completed, the flag signal being enabled before the first bus data signal is inputted and disabled before the bus data signal input is completed. According to the present invention, signal increase can be suppressed and power consumption can be reduced.
摘要翻译：一种用于减少待机模式下电流消耗的存储器件的输入缓冲器，包括用于通过总线输入连续总线数据信号并缓冲所输入的总线数据信号的总线输入缓冲器，以及用于响应系统时钟产生控制信号的标志缓冲器信号和表示总线数据输入时间点的标志信号，以在总线数据信号的第一个到达总线输入缓冲器之前操作总线输入缓冲器，并且允许总线输入缓冲器在之后立即进入待机模式总线数据信号输入完成，标志信号在总线数据信号输入完成之前被输入和禁止第一总线数据信号之前被使能。根据本发明，可以抑制信号增加并且能够降低功耗。

2. 发明授权

US6154073A Delay locked loop device of the semiconductor circuit 有权
标题翻译：半导体电路的延迟锁定环路装置
公开(公告)号：US6154073A
公开(公告)日：2000-11-28
申请号：US196121
申请日：1998-11-20
申请人： Jae Myoung Choi
发明人： Jae Myoung Choi
IPC分类号： G06F1/10 , G06F1/12 , G11C11/407 , G11C11/4076 , H03K5/13 , H03L7/081 , H03L7/089 , H03L7/00
CPC分类号： H03L7/0814 , H03L7/0891
摘要： Delay Locked Loop device generates an internal clock by receiving an external clock. Multiplexer is provided to receive N delay signals outputted from the first to Nth delay elements which receives the external clock. The Delay Locked Loop device generates the internal clock by selecting one of the N delay signals. The phase of the internal clock follows the phase of the external clock.
摘要翻译：延迟锁定环路设备通过接收外部时钟产生内部时钟。提供多路复用器以接收从接收外部时钟的第一至第N延迟元件输出的N个延迟信号。延迟锁定环路设备通过选择N个延迟信号之一来产生内部时钟。内部时钟的相位遵循外部时钟的相位。

3. 发明授权

US08831495B2 Fusing device and image forming apparatus having the same 有权
标题翻译：定影装置和具有该定影装置的图像形成装置
公开(公告)号：US08831495B2
公开(公告)日：2014-09-09
申请号：US13334898
申请日：2011-12-22
申请人： Hwan Hee Kim , Jae Myoung Choi , Dong Jin Seol
发明人： Hwan Hee Kim , Jae Myoung Choi , Dong Jin Seol
IPC分类号： G03G15/20
CPC分类号： G03G15/2025 , G03G2215/2035
摘要： A fusing device to reduce lubricant leakage, includes a fusing belt having a heat source placed therein, a pressure roller placed to apply pressure to an outer surface of the fusing belt, and a nip plate to support an inner surface of the fusing belt so as to define a fusing nip between the fusing belt and the pressure roller. The nip plate includes a stepped portion spaced apart from the inner surface of the fusing belt so as to define a space for accommodation of a lubricant applied to the inner surface of the fusing belt. The fusing device may further include a side frame to rotatably support a longitudinal end of the fusing belt. The side frame may be provided with a lubricant guide to guide the lubricant on the longitudinal end of the fusing belt toward the center of the fusing belt.
摘要翻译：一种用于减少润滑剂泄漏的定影装置，包括其中放置有热源的定影带，设置用于对定影带的外表面施加压力的压力辊和夹持板，以支撑定影带的内表面，以便以在定影带和压力辊之间限定定影辊隙。夹持板包括与定影带的内表面间隔开的阶梯部分，以便限定用于容纳施加到定影带的内表面的润滑剂的空间。定影装置还可以包括侧框架，以可旋转地支撑定影带的纵向端部。侧框架可以设置有润滑剂引导件，以将定影带的纵向端部上的润滑剂朝着熔合带的中心引导。

4. 发明授权

US08320796B2 Image forming apparatus 有权
标题翻译：图像形成装置
公开(公告)号：US08320796B2
公开(公告)日：2012-11-27
申请号：US12685446
申请日：2010-01-11
申请人： Kwoang Joe Seorl , Jae Myoung Choi , Jin Ho Park
发明人： Kwoang Joe Seorl , Jae Myoung Choi , Jin Ho Park
IPC分类号： G03G21/18
CPC分类号： G03G21/1842
摘要： Disclosed herein is an image forming apparatus including a main body; a developing unit detachably mounted on the main body and having a photoconductive medium; and a cover pivotably mounted on the main body to cover and support an outer end of the developing unit. The cover may comprises a latch engaged with the main body by one end thereof so that the cover supports the developing unit. A member that supports a shaft of the photoconductive medium may also be included. Because the member operates in association with the latch, opening and closing of the cover may be facilitated, accordingly also facilitating separation of the developing unit from the main body.
摘要翻译：本文公开了一种图像形成装置，包括主体; 显影单元，其可拆卸地安装在主体上并具有光导介质; 以及可枢转地安装在主体上以覆盖和支撑显影单元的外端的盖。盖可以包括通过其一端与主体接合的闩锁，使得盖支撑显影单元。还可以包括支撑感光介质轴的构件。由于构件与闩锁相关联地操作，因此可以方便地打开和关闭盖，因此也有利于显影单元与主体的分离。

5. 发明授权

US5768197A Redundancy circuit for semiconductor memory device 失效
标题翻译：半导体存储器件冗余电路
公开(公告)号：US5768197A
公开(公告)日：1998-06-16
申请号：US774318
申请日：1996-12-24
申请人： Jae Myoung Choi
发明人： Jae Myoung Choi
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G11C5/00
CPC分类号： G11C29/785
摘要： A redundancy circuit for a semiconductor memory device, comprising a first precharge transistor for transferring a precharge voltage to a first node in response to a first precharge signal, a second precharge transistor for transferring the precharge voltage transferred by the first precharge transistor to the first node in response to a second precharge signal, a first inverter for inverting a signal at the first node, an output terminal for transferring an output signal from the first inverter externally, a first NMOS transistor for transferring a supply voltage to the first node in response to a signal at the output terminal, a second inverter for inverting the second precharge signal, a second NMOS transistor for transferring a ground voltage to a second node in response to an output signal from the second inverter, a third NMOS transistor for transferring the ground voltage to the second node in response to the signal at the output terminal, a plurality of fourth NMOS transistors connected in parallel between the first and second nodes, for transferring a signal at the second node to the first node in response to an input address, and a plurality of fuses connected respectively between the first node and the fourth NMOS transistors, for programming a failed address.
摘要翻译：一种用于半导体存储器件的冗余电路，包括用于响应于第一预充电信号将预充电电压传送到第一节点的第一预充电晶体管，用于将由第一预充电晶体管传送的预充电电压传送到第一节点的第二预充电晶体管响应于第二预充电信号，用于将第一节点处的信号反相的第一反相器，用于从外部传送来自第一反相器的输出信号的输出端子，用于响应于第一NMOS晶体管将电源电压传送到第一节点在输出端子处的信号，用于反转第二预充电信号的第二反相器，用于响应于来自第二反相器的输出信号将接地电压传送到第二节点的第二NMOS晶体管，用于传送接地电压的第三NMOS晶体管响应于在输出端子处的信号到第二节点，多个第四NMOS晶体管在第一节点和第二节点之间并联连接，用于响应于输入地址将第二节点处的信号传送到第一节点，以及分别连接在第一节点和第四NMOS晶体管之间的多个熔丝，用于编程失败地址。

6. 发明申请

US20120170957A1 FUSING DEVICE AND IMAGE FORMING APPARATUS HAVING THE SAME 有权
标题翻译：熔接装置和具有该装置的图像形成装置
公开(公告)号：US20120170957A1
公开(公告)日：2012-07-05
申请号：US13339952
申请日：2011-12-29
申请人： Jae Hyuk LIM , Jae Myoung Choi , Sang Cheol Moon , Hyun Il Kim , Choong Kyu Park
发明人： Jae Hyuk LIM , Jae Myoung Choi , Sang Cheol Moon , Hyun Il Kim , Choong Kyu Park
IPC分类号： G03G15/20
CPC分类号： G03G15/2064 , G03G2215/2035
摘要： A fusing device and an image forming apparatus having the same are provided. The fusing device includes a position regulating device to regulate a position of a side frame which rotatably supports a fusing belt, thereby fixing a position of a fusing nip defined between the fusing belt, inside of which a heat source is placed, and a pressure roller arranged to face the fusing belt. The fusing device prevents shift of a recording medium delivery path due to deformation of the pressure roller.
摘要翻译：提供了一种定影装置和具有该定影装置的图像形成装置。定影装置包括位置调节装置，用于调节可转动地支撑定影带的侧框架的位置，从而固定限定在其内设有热源的定影带和压辊之间的定影辊隙的位置安排面对定影带。定影装置防止由于加压辊的变形引起的记录介质输送路径的移动。

7. 发明申请

US20100178075A1 IMAGE FORMING APPARATUS 有权
标题翻译：图像形成装置
公开(公告)号：US20100178075A1
公开(公告)日：2010-07-15
申请号：US12685446
申请日：2010-01-11
申请人： Kwoang Joe SEORL , Jae Myoung Choi , Jin Ho Park
发明人： Kwoang Joe SEORL , Jae Myoung Choi , Jin Ho Park
IPC分类号： G03G21/18
CPC分类号： G03G21/1842
摘要： Disclosed herein is an image forming apparatus including a main body; a developing unit detachably mounted on the main body and having a photoconductive medium; and a cover pivotably mounted on the main body to cover and support an outer end of the developing unit. The cover may comprises a latch engaged with the main body by one end thereof so that the cover supports the developing unit. A member that supports a shaft of the photoconductive medium may also be included. Because the member operates in association with the latch, opening and closing of the cover may be facilitated, accordingly also facilitating separation of the developing unit from the main body.
摘要翻译：本文公开了一种图像形成装置，包括主体; 显影单元，其可拆卸地安装在主体上并具有光导介质; 以及可枢转地安装在主体上以覆盖和支撑显影单元的外端的盖。盖可以包括通过其一端与主体接合的闩锁，使得盖支撑显影单元。还可以包括支撑感光介质轴的构件。由于构件与闩锁相关联地操作，因此可以方便地打开和关闭盖，因此也有利于显影单元与主体的分离。

8. 发明授权

US06460102B1 Semiconductor system having a master device and a slave device 失效
标题翻译：具有主设备和从设备的半导体系统
公开(公告)号：US06460102B1
公开(公告)日：2002-10-01
申请号：US09196118
申请日：1998-11-20
申请人： Jae Myoung Choi
发明人： Jae Myoung Choi
IPC分类号： G06F1300
CPC分类号： G06F13/4072
摘要： A semiconductor system having a master device and a slave device. The master device and the slave device are coupled together through the data bus and control signal line. The master device inputs a calibration signal to the slave device in response to the control signal. The voltage level of the data outputted from the slave device is corrected by the calibration operation.
摘要翻译：一种具有主设备和从设备的半导体系统。主设备和从设备通过数据总线和控制信号线耦合在一起。主设备响应于控制信号将校准信号输入到从设备。通过校准操作来校正从设备输出的数据的电压电平。

9. 发明授权

US5844447A Oscillator device generating signals of different cycles 失效
标题翻译：振荡器产生不同周期的信号
公开(公告)号：US5844447A
公开(公告)日：1998-12-01
申请号：US885834
申请日：1997-06-30
申请人： Jae Myoung Choi
发明人： Jae Myoung Choi
IPC分类号： H03B5/00 , H03K3/03 , H03K3/354 , H03K3/353
CPC分类号： H03K3/354 , H03K3/0315
摘要： An oscillating device is disclosed including a first ring oscillator having at least three odd inverters connected in series, an input terminal of the first of the inverters being connected with an output terminal of the last of the inverters, and applying an output signal of the last inverter to a first buffer's input terminal, thus producing a signal of the first cycle; the first buffer connected with the output terminal of the first ring oscillator's last inverter, having at least two even inverters connected in series, and buffering an output signal of the last inverter to produce it to outside; a second ring oscillator having at least three odd delay devices connected in series, wherein a power supply of each delay device is connected with the output terminal of each of the first ring oscillator's corresponding inverters, and an output terminal of the last of the delay devices is connected with an input terminal of the first of the delay devices, thus producing a signal of the second cycle, larger than the first cycle, to an input terminal of a second buffer; and the second buffer connected with the output terminal of the second ring oscillator's last delay device, having at least two even inverters connected in series, and buffering an output signal of the last delay device.
摘要翻译：公开了一种振荡器件，包括具有串联连接的至少三个奇数反相器的第一环形振荡器，第一反相器的输入端与最后一个反相器的输出端相连，并施加最后一个反相器的输出信号逆变器到第一缓冲器的输入端，从而产生第一个周期的信号; 第一缓冲器与第一环形振荡器的最后一个反相器的输出端连接，具有串联连接的至少两个偶数反相器，并且缓冲最后一个反相器的输出信号以产生到外部; 具有串联连接的至少三个奇数延迟器件的第二环形振荡器，其中每个延迟器件的电源与第一环形振荡器相应的反相器中的每一个的输出端连接，并且最后一个延迟器件的输出端与第一延迟装置的输入端连接，从而产生大于第一周期的第二周期的信号给第二缓冲器的输入端; 第二缓冲器与第二环形振荡器的最后延迟装置的输出端连接，具有串联连接的至少两个偶数反相器，并缓冲最后延迟装置的输出信号。

10. 发明授权

US5831922A Semiconductor device having a refresh device of a noise reduction type 失效
标题翻译：具有降噪型刷新装置的半导体装置
公开(公告)号：US5831922A
公开(公告)日：1998-11-03
申请号：US953344
申请日：1997-10-17
申请人： Jae Myoung Choi
发明人： Jae Myoung Choi
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A semiconductor device having a refresh device of a noise reduction type lowers a peak current value by sequentially performing refresh operations about a plurality of dynamic RAMs (DRAMs) in a system having a daisy chain structure, thereby reducing noises generated from the system.
摘要翻译：具有降噪型刷新装置的半导体装置通过在具有菊花链结构的系统中顺序执行关于多个动态RAM（DRAM）的刷新操作来降低峰值电流值，从而减少从系统产生的噪声。

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