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1. 发明授权

US08929154B2 Layout of memory cells 有权
标题翻译：存储单元布局
公开(公告)号：US08929154B2
公开(公告)日：2015-01-06
申请号：US13267235
申请日：2011-10-06
申请人： Jacklyn Chang , Derek C. Tao , Yukit Tang , Kuoyuan (Peter) Hsu
发明人： Jacklyn Chang , Derek C. Tao , Yukit Tang , Kuoyuan (Peter) Hsu
IPC分类号： G11C7/10 , G11C7/18 , H01L27/02 , G11C11/412 , G11C11/413 , H01L27/11
CPC分类号： G11C7/18 , G11C11/412 , G11C11/413 , H01L27/0207 , H01L27/1104
摘要： A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.
摘要翻译：半导体结构包括第一带状电池，第一读取端口和第一VSS端子。第一带状电池具有第一带电池VSS区域。第一读取端口具有第一读取端口VSS区域，第一读取端口读取位线区域和第一读取端口聚合区域。第一VSS端子被配置为电耦合第一带电池VSS区域和第一读取端口VSS区域。

2. 发明授权

US08339890B2 Memory leakage and data retention control 有权
标题翻译：内存泄漏和数据保留控制
公开(公告)号：US08339890B2
公开(公告)日：2012-12-25
申请号：US12788860
申请日：2010-05-27
申请人： Kuoyuan (Peter) Hsu , Yukit Tang , Jacklyn Chang
发明人： Kuoyuan (Peter) Hsu , Yukit Tang , Jacklyn Chang
IPC分类号： G11C5/14
CPC分类号： G11C5/148 , G11C11/413
摘要： A circuit with leakage and data retention control includes at least one memory cell in a first memory array. The at least one memory cell is coupled to a first power supply voltage and a virtual ground. The circuit includes a current source and an NMOS transistor. The drain of the NMOS transistor is coupled to the virtual ground and the gate of the NMOS transistor is coupled to the current source.
摘要翻译：具有泄漏和数据保持控制的电路包括第一存储器阵列中的至少一个存储单元。所述至少一个存储单元耦合到第一电源电压和虚拟地。该电路包括电流源和NMOS晶体管。 NMOS晶体管的漏极耦合到虚拟接地，并且NMOS晶体管的栅极耦合到电流源。

3. 发明授权

US08704376B2 Layout of memory strap cell 有权
标题翻译：记忆带细胞布局
公开(公告)号：US08704376B2
公开(公告)日：2014-04-22
申请号：US13443467
申请日：2012-04-10
申请人： Jacklyn Chang , Evan Yong Zhang , Derek C. Tao , Kuoyuan (Peter) Hsu
发明人： Jacklyn Chang , Evan Yong Zhang , Derek C. Tao , Kuoyuan (Peter) Hsu
IPC分类号： H01L23/498
CPC分类号： H01L27/1104 , H01L27/0207
摘要： A layout structure includes a substrate, a well, a first dopant area, a second dopant area, a first poly region, a third dopant area, a fourth dopant area, and a second poly region. The well is in the substrate. The first poly region is in between the first dopant area and the second dopant area. The second poly region is in between the third dopant area and the fourth dopant area. The first dopant area, the second dopant area, the third dopant area, and the fourth dopant area are in the well. The first dopant area is configured to serve as a source of a transistor and to receive a first voltage value from a first power supply source. The well is configured to serve as a bulk of the transistor and to receive a second voltage value from a second power supply source.
摘要翻译：布局结构包括衬底，阱，第一掺杂区，第二掺杂区，第一多晶区，第三掺杂区，第四掺杂区和第二多晶区。井在底层。第一多晶硅区位于第一掺杂区和第二掺杂区之间。第二聚合区位于第三掺杂区和第四掺杂区之间。第一掺杂剂区域，第二掺杂剂区域，第三掺杂剂区域和第四掺杂剂区域在井中。第一掺杂剂区域被配置为用作晶体管的源极并且从第一电源接收第一电压值。阱被配置为用作晶体管的体积并从第二电源接收第二电压值。

4. 发明授权

US08450778B2 Method and apparatus for memory cell layout 有权
标题翻译：用于存储单元布局的方法和装置
公开(公告)号：US08450778B2
公开(公告)日：2013-05-28
申请号：US12862387
申请日：2010-08-24
申请人： Jacklyn Chang , Kuoyuan Hsu , Derek C. Tao
发明人： Jacklyn Chang , Kuoyuan Hsu , Derek C. Tao
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/0207
摘要： A semiconductor device has first and second interconnect structures in first and second columns, respectively, of an array. Each of the first and second interconnect structures has a reference voltage node and first, second, third, and fourth conductors that are coupled to each other and formed at a first layer, a second layer, a third layer, and a fourth layer, respectively, over a substrate having a plurality of devices defining a plurality of bit cells. The reference voltage node of each interconnect structure provides a respectively separate reference voltage to a bit cell corresponding to said interconnect structure. None of the first, second, third, and fourth conductors in either interconnect structure is connected to a corresponding conductor in the other interconnect structure. The second layer is above the first layer, the third layer is above the second layer, and the fourth layer is above the third layer.
摘要翻译：半导体器件分别在阵列的第一和第二列中具有第一和第二互连结构。第一和第二互连结构中的每一个具有参考电压节点和彼此耦合并分别形成在第一层，第二层，第三层和第四层上的第一，第二，第三和第四导体在具有限定多个位单元的多个器件的衬底上。每个互连结构的参考电压节点向对应于所述互连结构的位单元提供分别分离的参考电压。在互连结构中的第一，第二，第三和第四导体中的任一个都不连接到另一个互连结构中的相应导体。第二层在第一层之上，第三层位于第二层之上，第四层位于第三层之上。

5. 发明授权

US09280633B2 Content addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US09280633B2
公开(公告)日：2016-03-08
申请号：US14279406
申请日：2014-05-16
申请人： Young Seog Kim , Kuoyuan Hsu , Jacklyn Chang
发明人： Young Seog Kim , Kuoyuan Hsu , Jacklyn Chang
IPC分类号： G11C15/00 , G06F17/50 , G11C15/04 , H03K19/20
CPC分类号： G06F17/5072 , G11C15/04 , H03K19/20
摘要： A method of designing a content-addressable memory (CAM) includes associating CAM cells with a summary circuit. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. Logic gates in at least one of the first level of logic gates or the second level of logic gates are selected to have an odd number of input pins so that an input pin and an output pin share a layout sub-slot.
摘要翻译：设计内容寻址存储器（CAM）的方法包括将CAM单元与汇总电路相关联。汇总电路包括第一级逻辑门和第二级逻辑门。第一级逻辑门具有各自被配置为接收多个CAM单元中对应的一个的单元的输出的输入。逻辑门的第二级具有各自被配置为接收第一级逻辑门的对应的一个的输出的输入。选择第一级逻辑门或第二级逻辑门中的至少一个的逻辑门具有奇数个输入引脚，使得输入引脚和输出引脚共享布局子时隙。

6. 发明授权

US08760900B2 Content addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US08760900B2
公开(公告)日：2014-06-24
申请号：US13770436
申请日：2013-02-19
申请人： Young Seog Kim , Kuoyuan Hsu , Jacklyn Chang
发明人： Young Seog Kim , Kuoyuan Hsu , Jacklyn Chang
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G06F17/5072 , G11C15/04 , H03K19/20
摘要： A memory includes a plurality of content-addressable memory (CAM) cells and a summary circuit associated with the plurality of CAM cells. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates.
摘要翻译：存储器包括多个可内容寻址存储器（CAM）单元和与多个CAM单元相关联的汇总电路。汇总电路包括第一级逻辑门和第二级逻辑门。第一级逻辑门具有各自被配置为接收多个CAM单元中对应的一个的单元的输出的输入。逻辑门的第二级具有各自被配置为接收第一级逻辑门的对应的一个的输出的输入。

7. 发明授权

US08395920B2 Content addressable memory design 有权
标题翻译：内容可寻址内存设计
公开(公告)号：US08395920B2
公开(公告)日：2013-03-12
申请号：US12788924
申请日：2010-05-27
申请人： Young Seog Kim , Kuoyuan Hsu , Jacklyn Chang
发明人： Young Seog Kim , Kuoyuan Hsu , Jacklyn Chang
IPC分类号： G11C15/00
CPC分类号： G06F17/5072 , G11C15/04 , H03K19/20
摘要： A static CAM includes a plurality of entries E each including a number of CAM cells B and a summary S. Each CAM cell B is associated with a memory cell M and a comparator C. Generally, the CAM receives as input i number of lookup data lines. When data is received, memory cells M provide compared data for corresponding comparators C in CAM cells B to compare the compared data to the received data. If all compared data match all received data lines for an entry, then there is a hit for that entry. But if any compared data does not match the corresponding data line, then there is a miss for that line and therefore a miss for that entry. Depending on applications, the CAM returns an address if there is a hit for one or a plurality of entries.
摘要翻译：静态CAM包括多个条目E，每个条目E包括多个CAM单元B和概要S.每个CAM单元B与存储单元M和比较器C相关联。通常，CAM接收到i个查找数据线条。当接收到数据时，存储器单元M提供CAM单元B中对应的比较器C的比较数据，以将比较的数据与接收到的数据进行比较。如果所有比较的数据匹配所有接收到的数据行的条目，则该条目的命中。但是，如果任何比较的数据与相应的数据行不匹配，那么该行有一个缺失，因此该条目的缺失。根据应用程序，如果有一个或多个条目的命中，CAM将返回一个地址。

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