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1. 发明授权

US06826720B2 Testing board for semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory 有权
标题翻译：用于半导体存储器的测试板，半导体存储器的测试方法和制造半导体存储器的方法
公开(公告)号：US06826720B2
公开(公告)日：2004-11-30
申请号：US09994638
申请日：2001-11-28
申请人： Iwao Suzuki , Shuji Kikuchi , Fumie Kobayashi , Hideyuki Aoki
发明人： Iwao Suzuki , Shuji Kikuchi , Fumie Kobayashi , Hideyuki Aoki
IPC分类号： G11C2900
CPC分类号： G11C29/56 , G11C29/10
摘要： A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.
摘要翻译：使用ALPG的测试电路安装在测试板中，其中安装半导体存储器的插座作为板中要测试的器件，并且在测试电路中提供用于存储用于产生随机模式的数据表的易失性存储器，使得除了使用由ALPG生成的规则性的测试图案的测试之外，还使用数据表来执行使用不规则的测试图案的测试。

2. 发明授权

US07225372B2 Testing board for semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory 有权
标题翻译：用于半导体存储器的测试板，半导体存储器的测试方法和制造半导体存储器的方法
公开(公告)号：US07225372B2
公开(公告)日：2007-05-29
申请号：US10949192
申请日：2004-09-27
申请人： Iwao Suzuki , Shuji Kikuchi , Fumie Kobayashi , Hideyuki Aoki
发明人： Iwao Suzuki , Shuji Kikuchi , Fumie Kobayashi , Hideyuki Aoki
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C29/10
摘要： A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.
摘要翻译：使用ALPG的测试电路安装在测试板中，其中安装半导体存储器的插座作为板中要测试的器件，并且在测试电路中提供用于存储用于产生随机模式的数据表的易失性存储器，使得除了使用由ALPG生成的规则性的测试图案的测试之外，还使用数据表来执行使用不规则的测试图案的测试。

3. 发明申请

US20050044458A1 Testing board for semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory 有权
标题翻译：用于半导体存储器的测试板，半导体存储器的测试方法和制造半导体存储器的方法
公开(公告)号：US20050044458A1
公开(公告)日：2005-02-24
申请号：US10949192
申请日：2004-09-27
申请人： Iwao Suzuki , Shuji Kikuchi , Fumie Kobayashi , Hideyuki Aoki
发明人： Iwao Suzuki , Shuji Kikuchi , Fumie Kobayashi , Hideyuki Aoki
IPC分类号： G01R31/30 , G01R31/28 , G01R31/3183 , G11C29/10 , G11C29/56 , G11C7/00 , G11C29/00
CPC分类号： G11C29/56 , G11C29/10
摘要： A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.
摘要翻译：使用ALPG的测试电路安装在测试板中，其中安装半导体存储器的插座作为板中要测试的器件，并且在测试电路中提供用于存储用于产生随机模式的数据表的易失性存储器，使得除了使用由ALPG生成的规则性的测试图案的测试之外，还使用数据表来执行使用不规则的测试图案的测试。

4. 发明授权

US07774667B2 Semiconductor device and data processing system 失效
标题翻译：半导体器件和数据处理系统
公开(公告)号：US07774667B2
公开(公告)日：2010-08-10
申请号：US12054366
申请日：2008-03-24
申请人： Tatsuya Saito , Kaname Yamasaki , Iwao Suzuki , Takeshi Bingo , Keiichi Horie
发明人： Tatsuya Saito , Kaname Yamasaki , Iwao Suzuki , Takeshi Bingo , Keiichi Horie
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/1201 , G11C2029/3602
摘要： The test design cost of a circuit capable of accessing an external memory is reduced. There is included a built-in self-test circuit for use in testing an external memory separately from a memory controller for performing memory control in response to an access request to the external memory capable of being coupled to a memory interface, and a TAP controller is used to control the built-in self-test circuit and referring to a test result. There is adopted a multiplexer for switchably selecting the memory controller or the built-in self-test circuit as a circuit for coupling to the memory interface in accordance with control information externally inputted through the TAP controller. The built-in self-test circuit programmably generates and outputs a pattern for a memory test in accordance with an instruction inputted through the TAP controller, and compares data read from the external memory with an expected value.
摘要翻译：能够访问外部存储器的电路的测试设计成本降低。包括内置自检电路，用于独立于存储器控制器测试外部存储器，用于响应于能够耦合到存储器接口的外部存储器的访问请求执行存储器控制，以及TAP控制器用于控制内置自检电路并参考测试结果。采用多路复用器，根据外部通过TAP控制器输入的控制信息，可选择存储控制器或内置自检电路作为耦合到存储器接口的电路。内置的自检电路可编程地根据通过TAP控制器输入的指令产生和输出用于存储器测试的模式，并且将从外部存储器读取的数据与预期值进行比较。

5. 发明申请

US20080263414A1 SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM 失效
标题翻译：半导体器件和数据处理系统
公开(公告)号：US20080263414A1
公开(公告)日：2008-10-23
申请号：US12054366
申请日：2008-03-24
申请人： Tatsuya Saito , Kaname Yamasaki , Iwao Suzuki , Takeshi Bingo , Keiichi Horie
发明人： Tatsuya Saito , Kaname Yamasaki , Iwao Suzuki , Takeshi Bingo , Keiichi Horie
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/16 , G11C29/1201 , G11C2029/3602
摘要： The test design cost of a circuit capable of accessing an external memory is reduced. There is included a built-in self-test circuit for use in testing an external memory separately from a memory controller for performing memory control in response to an access request to the external memory capable of being coupled to a memory interface, and a TAP controller is used to control the built-in self-test circuit and referring to a test result. There is adopted a multiplexer for switchably selecting the memory controller or the built-in self-test circuit as a circuit for coupling to the memory interface in accordance with control information externally inputted through the TAP controller. The built-in self-test circuit programmably generates and outputs a pattern for a memory test in accordance with an instruction inputted through the TAP controller, and compares data read from the external memory with an expected value.
摘要翻译：能够访问外部存储器的电路的测试设计成本降低。包括内置自检电路，用于独立于存储器控制器测试外部存储器，用于响应于能够耦合到存储器接口的外部存储器的访问请求执行存储器控制，以及TAP控制器用于控制内置自检电路并参考测试结果。采用多路复用器，根据外部通过TAP控制器输入的控制信息，可选择存储控制器或内置自检电路作为耦合到存储器接口的电路。内置的自检电路可编程地根据通过TAP控制器输入的指令产生和输出用于存储器测试的模式，并且将从外部存储器读取的数据与预期值进行比较。

6. 发明授权

US09469897B2 Thin film forming apparatus and thin film forming method 有权
标题翻译：薄膜形成装置和薄膜形成方法
公开(公告)号：US09469897B2
公开(公告)日：2016-10-18
申请号：US13991667
申请日：2011-11-29
申请人： Yoshimasa Chikama , Iwao Suzuki
发明人： Yoshimasa Chikama , Iwao Suzuki
IPC分类号： C23C14/00 , C23C14/35 , C23C14/08 , C23C14/56 , H01J37/34
CPC分类号： C23C14/352 , C23C14/08 , C23C14/564 , H01J37/3417 , H01J37/3429 , H01J37/3447 , H01J37/3455
摘要： A thin film forming apparatus includes a substrate holding portion and a target portion. The target portion has a plurality of targets arranged at predetermined intervals and parallel to a substrate held by the substrate holding portion. The substrate holding portion is configured to move the substrate parallel to the target portion. A shield portion configured to block sputtered particles flying from the target portion is placed on the target portion side of the substrate so as to face a gap between adjoining ones of the targets.
摘要翻译：薄膜形成装置包括基板保持部和目标部。目标部分具有以预定间隔布置并平行于由基板保持部保持的基板的多个目标。基板保持部构造成使基板平行于目标部移动。被配置为阻挡从目标部分飞出的溅射颗粒的屏蔽部分被放置在基板的目标部分侧上，以面对相邻的目标之间的间隙。

7. 发明申请

US20140021037A1 THIN FILM FORMING APPARATUS AND THIN FILM FORMING METHOD 有权
标题翻译：薄膜成型装置和薄膜成型方法
公开(公告)号：US20140021037A1
公开(公告)日：2014-01-23
申请号：US13991667
申请日：2011-11-29
申请人： Yoshimasa Chikama , Iwao Suzuki
发明人： Yoshimasa Chikama , Iwao Suzuki
IPC分类号： C23C14/35
CPC分类号： C23C14/352 , C23C14/08 , C23C14/564 , H01J37/3417 , H01J37/3429 , H01J37/3447 , H01J37/3455
摘要： A thin film forming apparatus includes a substrate holding portion and a target portion. The target portion has a plurality of targets arranged at predetermined intervals and parallel to a substrate held by the substrate holding portion. The substrate holding portion is configured to move the substrate parallel to the target portion. A shield portion configured to block sputtered particles flying from the target portion is placed on the target portion side of the substrate so as to face a gap between adjoining ones of the targets.
摘要翻译：薄膜形成装置包括基板保持部和目标部。目标部分具有以预定间隔布置并平行于由基板保持部保持的基板的多个目标。基板保持部构造成使基板平行于目标部移动。被配置为阻挡从目标部分飞出的溅射颗粒的屏蔽部分被放置在基板的目标部分侧上，以面对相邻的目标之间的间隙。

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